Thank you Tim. I'm glad that you share the idea of importance of the worst case solution. Personally, I was wondering for some time why such powerful type of analysis (worst case analysis) didn't gain enough popularity compared to plain time domain and statistical. My only answer to that was that the designers always wanted to take into account many effects going beyond assumptions of LTI. Still, some types of non-LTI behavior do not prevent us from finding worst case eye, however of course this makes the algorithm more complicated. When we started re-analyzing some earliest designs considering asymmetry (just one factor contributing into non-LTI), we get surprisingly many cases in which asymmetry - as we now understand - should not be neglected. If it is still interesting for you and Joel how the constrained worst case pattern performs, I can build and send it back to you to check. The only thing I need to know is your system's step response (if asymmetry is needed, then two responses, rising and falling) and bit interval. Vladimir -----Original Message----- From: thollis@xxxxxxxxxx [mailto:thollis@xxxxxxxxxx] Sent: Monday, March 09, 2009 8:22 AM To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx Subject: RE: [SI-LIST] Re: How to simulate worse case eye Thanks Vladimir - I was just trying to provide a quick solution for Joel. We went into a little more depth off-line. I'm aware of the issues with nonlinearity and time-variance. I actually submitted a paper to DesignCon this last year addressing many of the issues and potential error observed when applying these types of statistical methods to nonlinear systems, but it was rejected - perhaps it was too controversial. Anyway, thanks for adding to the discussion. Tim -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Dmitriev-Zdorov, Vladimir Sent: Saturday, March 07, 2009 8:02 AM To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Re: How to simulate worse case eye Tim/Joel, Perhaps, I should have given more details in my previous reply. Yes, the paper of Brian Casper, and even some earlier works give us a method of building an unconstrained worst case pattern; that is relatively simple. I would also recommend reading this paper as an excellent introduction into the topic. However, this approach does not answer all practical needs, including the following. 1. Encoded worst case pattern. In many important cases the unconstrained worst case solution does not have much value. If e.g. the SERDES channel includes series capacitor(s), we know that the eye will be closed by sufficiently long series of logical 'ones' or 'zeros'. The longer is a series of identical bits, the more closed the eye becomes. In this sense, there is no 'worst' unconstrained solution, unless the pattern length is limited. Of course, in such channels only encoded binary inputs are allowed (8b10b or some others), with their imparity and running length constraints, for which the idea of 'worst case pattern' makes a perfect sense. There exists a solution for such case in HL. 2. Some types of non-LTI behavior. For example, in many cases the responses to rising and falling transitions are not symmetrical, that means their sum R(t) + F(t) is not identical constant. There are several sources of this phenomenon: (a) persistent time shift between R/F transitions (DCD), (b) asymmetry of PU and PD I-V or timing characteristics in a single ended channel, or (c) partial conversion of near end common signal into far end differential signal, that may occur even with identical differential buffers, if linear part of the channel is not ideally symmetric (creates differential skew). In the recent Mentor/Tek paper "New methods of measuring the performance of equalized serial data links and correlation of performance measures across the design flow..." from DesignCon2009 we considered worst case solutions, including cases (1), (2) and combination of (1) and (2). > > > > Joel, I'm sure there will be no shortage of recommendations here, but here's my contribution: It's pretty easy to determine the worst case pattern for a single route, assuming the system is linear-time-invariant. 1. Start by generating the pulse response of the system. 2. Then sample the response at UI intervals from the Peak or cursor sample, or just eyeball the ISI at these intervals. 3. Based on the direction or polarity of the ISI terms, and their relative distances from the cursor (in UI), you can determine what input pattern can be used to maximize the combined contributions of the ISI terms. Positive-going ISI terms eat away from the nominal zero level, and negative-going ISI terms eat away from the nominal one level. 4. You can then move your cursor away from the peak of the pulse response and repeat the process to determine patterns targeting points across the width of the eye if desired. If you haven't read it, check out Bryan Casper's paper describing the use of Peak Distortion analysis to generate Worst Case Eyes. It doesn't explicitly tell you how to generate the worst case pattern, but it may inspire you. B.K. Casper, et al, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes." If you've got IEEE access: http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber15043&isnumber!8 31 Tim Hollis DRAM Design Micron Technology, Inc. -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Joel Brown Sent: Friday, March 06, 2009 3:35 PM To: SI-LIST@xxxxxxxxxxxxx Subject: [SI-LIST] How to simulate worse case eye I was watching a webinar by Mentor on Hyperlynx and how they can quickly generate a prbs pattern that results in a worse case eye diagram. They said without this feature it could take days or even years of simulation to do this. I do most of my simulation in hspice since most of my models are based in Hspice. Is there a way to do what Mentor is claiming in Hspice by generating a certain pattern? I have been using the following code for a prbs sequence: vin inr vcm LFSR(0.1 -0.1 1n 5ps 5ps + 'data_rate' 1 [7,4,1] rout=0) vinn innr vcm LFSR(-0.1 0.1 1n 5ps 5ps + 'data_rate' 1 [7,4,1] rout=0) Thanks - Joel ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu