Posts for si-list, 01-2009

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  1. » [SI-LIST] Doing your own EMI Analysis, V S
  2. » [SI-LIST] Re: ground planes at top / bottom layer, Lee Ritchey
  3. » [SI-LIST] Re: Bulk capacitor decoupling, liuluping 41830
  4. » [SI-LIST] Re: mode conversion myth, liuluping 41830
  5. » [SI-LIST] 一絲不掛的虹蘭展現出無與倫比的出塵的美, f83118
  6. » [SI-LIST] Re: Solder mask, liuluping 41830
  7. » [SI-LIST] Re: Some food for thought, Schumacher, Richard (HSTD Signal Integrity)
  8. » [SI-LIST] 3D-em simulation and terminations: macromodelling, Istvan Nagy
  9. » [SI-LIST] Re: 3D-em simulation and terminations: macromodelling, Dmitriev-Zdorov, Vladimir
  10. » [SI-LIST] Manufacturing Issues, Thompson, Gary D (Gary)
  11. » [SI-LIST] 65 Ohm compact PCI impedance, Sexton, Brian M. \(US SSA\)
  12. » [SI-LIST] stripline with unconnected reference planes, Sexton, Brian M. \(US SSA\)
  13. » [SI-LIST] Re: 65 Ohm compact PCI impedance, Lee Ritchey
  14. » [SI-LIST] Senior Staff Signal Integrity Opening (Juniper Networks), Luong Hoang
  15. » [SI-LIST] parasitic elements of SMD resistors, jan . vercammen1
  16. » [SI-LIST] 1) Winnersh UK: Free joint seminar from Agilent, Xilinx, Elpida, MathWorks, NXP 2) Free Agilent Webcast in European time zone, colin_warwick
  17. » [SI-LIST] Re: Where are IBIS models with SSO support ?, Cortex Y.C. Chen
  18. » [SI-LIST] mEEt and gEEk 3.0, Julian Ferry
  19. » [SI-LIST] Are there any protection device forum? Who know?, simon zhou
  20. » [SI-LIST] Discussion for IBIS modeling, Lijun
  21. » [SI-LIST] Ask for IBIS modeling, Lijun
  22. » [SI-LIST] OTA ouput noise, chao wang
  23. » [SI-LIST] IBIS Model Using Package Model Error, Chris . McGrath
  24. » [SI-LIST] Re: IBIS Model Using Package Model Error, Chris . McGrath
  25. » [SI-LIST] S11 and S21 for PCB trace with different dielectic think, John Kwan
  26. » [SI-LIST] Characteristic Impedance mesurement on PCB, padma gundala
  27. » [SI-LIST] Contract Work, Jory McKinley
  28. » [SI-LIST] my first SF novel now on Amazon, eric bogatin
  29. » [SI-LIST] VSWR using the TDR Measurements., padma gundala
  30. » [SI-LIST] IBIS Model Survey, Timothy Coyle
  31. » [SI-LIST] ICMCHK1 version 1.1.3 available!, Mirmak, Michael
  32. » [SI-LIST] Vote in the DesignCon Video Contest, colin_warwick
  33. » [SI-LIST] The Implications of Nonmonotonic Transitions, tucsonAz
  34. » [SI-LIST] AMD Contact, wjcsongr
  35. » [SI-LIST] HFNews letter, Doug Smith
  36. » [SI-LIST] link error in HFNews, Doug Smith
  37. » [SI-LIST] Re: mEEt and gEEk 3.0, Julian Ferry
  38. » [SI-LIST] Failed Tantalum capacitors - package hermeticity compromised, Salkow, Steven
  39. » [SI-LIST] Training Classes - Designing for Signal Integrity with Advanced Design System - Santa Clara CA February 24-27, colin_warwick
  40. » [SI-LIST] Re: Training Classes - Designing for Signal Integrity with Advanced Design System - Santa Clara CA February 24-27, colin_warwick
  41. » [SI-LIST] Multi-transmission line Zo, Jennifer Maharani
  42. » [SI-LIST] BGA vias outside the package, Ryan Sequeira
  43. » [SI-LIST] Agenda, IBIS Summit at DesignCon for Feb. 5, 2009, Mirmak, Michael
  44. » [SI-LIST] hspice erroring out, Danish Jawed
  45. » [SI-LIST] Teraspeed at DesignCon, Scott McMorrow
  46. » [SI-LIST] January Issue of XrossTalk Magazine Available, Timothy Coyle
  47. » [SI-LIST] PCI Express CLB compliance waveform, Joel Brown
  48. » [SI-LIST] New content available on beTheSignal.com, eric bogatin