[SI-LIST] Re: The Implications of Nonmonotonic Transitions
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: "tucsonAz" <tucsonaz111@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 21 Jan 2009 07:36:32 -0000
hi
you mean input setup time of the receiver?
at the receiver chip, the input data is clocked to a clock signal, or to a
write/read strobe rising edge. input setup times are related to one of these
edges on your board.
If the data does not have stable value inside the input setup time region,
then the device can detect it as 0 or 1, so completely random.
if the non monoton edge is outside the input setup / input hold regions,
then it should be OK.
you should also consider clock jitter and PCB propagating delays as well...,
not just the input su/h parameters, so do a timing analysis, to determine
the safe region where your signal is allowed to be non-monoton.
read this: http://focus.ti.com/lit/an/spra839a/spra839a.pdf
or this: http://www.syncad.com/pdf-docs/paper_cc_timing_everything_2003.pdf
or this:
http://www.amazon.com/Timing-Analysis-Simulation-Integrity-Engineers/dp/B00132S6X2
Istvan Nagy
Concurrent Technologies Plc, UK
----- Original Message -----
From: "tucsonAz" <tucsonaz111@xxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, January 21, 2009 4:17 AM
Subject: [SI-LIST] The Implications of Nonmonotonic Transitions
>I have a nonmonotonic transition on a processor˘s data line.
>
> Example:
> On a rising edge the signal passes the Vih(min), then back below it, and
> then again back above Vih(min). Termination may not be possible due to
> packaging constraints and the vendor will most likely only endorse an
> ideal square wave.
>
> The timing concern is that this ringing from a reflection would push into
> the setup time. However, the signal is stable before the required setup
> time of the interface, therefore, no impact.
>
> The signal integrity concern is that does this nonmonotonic transition
> have any impact to the LVCMOS (not sstl) at the receiving end? Even though
> the signal is an acceptable high voltage at the setup time.
>
> I have looked back through my device physics books from school attempting
> to find what impacts nonmonotonic transitions present to CMOS with no
> success. I have done web searches only finding papers talking about the
> results on the timing margin or leading into termination techniques.
>
> Are nonmonotonic transitions acceptable to CMOS outside of setup times?
> Can anyone suggest further reading sources?
>
> Your help is appreciated,
> Joe Engineer
>
>
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