[SI-LIST] Re: BGA vias outside the package
- From: Cosmin Iorga <ci249534@xxxxxxxxx>
- To: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Wed, 28 Jan 2009 16:19:16 -0800 (PST)
Scott,
I agree the microstrip structure and equations exist always when a trace is
routed above a plane. However, the current distribution may sometimes change
the characteristic impedance. For example when a trace is routed across a
split power plane the characteristic impedance increases due to the
discontinuity in the return current path.
Cosmin Iorga
NoiseCoupling.com
--- On Wed, 1/28/09, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Subject: Re: [SI-LIST] Re: BGA vias outside the package
To: "Cosmin Iorga" <ci249534@xxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx, "V S" <for_si2003@xxxxxxxxx>
Date: Wednesday, January 28, 2009, 2:21 PM
Cosmin
With all due respect, a microstrip formula for power traces sure can be used.
As long as the microstrip power and ground traces are above a plane, they are
transmission lines and can be decomposed as such. This is no different than
performing a PEEC decomposition. There will be transition issues at the
boundaries between the trace and the parallel plates of the power system, but
at these frequencies they are minimal. Will there be error? Yes, but as a
first approximation, the microstrip traces will add incremental inductance (and
therefore incremental noise) to the power system. If you want to worst case
the design, then the microstrip analysis can be performed with the reference
plane maximally far away from the trace (say the thickness of the board).
I am, of course, assuming that the remainder of the power delivery network is
modeled for via, spreading inductance, and capacitor inductance, using
well-known analytical methods, as described in many papers.
http://home.att.net/~istvan.novak/papers.html
http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf
http://www.teraspeed.com/papers/DC08_FullWaveCapacitorModeling_paper.pdf
http://www.teraspeed.com/papers/DC08_FullWaveCapacitorModeling_pres.pdf
http://www.teraspeed.com/papers/TF7_Bypass%20capacitor_inductance.pdf
http://www.teraspeed.com/papers/TF7_Bypass%20capacitor_inductance.pdf
http://www.teraspeed.com/papers/stack_up_vias_pdn_public.pdf
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Cosmin Iorga wrote:
I don't think the microstrip formula can be used for the 1.8V and 3.3V traces,
since the return current does not flow through the underneath plane. The
return current flows through the ground trace, so I suggest that an evaluation
of the loop inductance would give more accurate results than the microstrip
analysis.
Cosmin Iorga,
NoiseCoupling.com
--- On Wed, 1/28/09, V S <for_si2003@xxxxxxxxx> wrote:
From: V S <for_si2003@xxxxxxxxx>
Subject: [SI-LIST] Re: BGA vias outside the package
To: si-list@xxxxxxxxxxxxx
Date: Wednesday, January 28, 2009, 1:17 PM
Scott,
First I will complement your answer by adding -
1. Your have 4 pins on 1.8V rail. Assuming the four traces coming from the four
balls have no coupling the total inductance will be equivalent to the parallel
combination of the inductance.
2. Find the change in current dI expected in your 1.8V rail. IF dV is the
maximum change in the voltage that your 1.8V rail can tolerate then the maximum
tolerable impedance Z is given by dV/dI.
3. Make sure that the impedance across all the frequencies as calculated in the
Scott's suggestion is less than this Z.
You will need to repeat the things for your 3.3V rail. For calculating dI, take
into account the maximum current consumption and the take into account current
due to charging the all IO pins simultaneously. If C is the capacitive load, and
if there are N IO pins, then this switching current can be gives as NCdV/dT...
You
should be able to find C on the datasheet. dV/dT can also be found on the
datasheet. N is the maximum number of the IO pins. This switching current should
be applicable to 3.3V supply. I am not sure about 1.8V. I believe, 1.8V is only
the core voltage with not IO.
This will give you a pass or fail answer - or a ball park number. If you can
achieve the result with you existing design that is good. Otherwise, increase
the number of capacitors, use reduced series inductance capacitors. Recalculate
the check if you are meeting the required impedance target.
Vikas Shukla
--- On Wed, 1/28/09, Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
From: Scott McMorrow <scott@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: BGA vias outside the package
To:
Cc: si-list@xxxxxxxxxxxxx
Date: Wednesday, January 28, 2009, 12:43 PM
Ryan
Use a 2D field solver to compute the impedance of the trace
you'll use
to connect the outer layer planes to the balls. If
microstrip, prop
delay is approximately 150 ps/in. Once you know your trace
impedance
you can compute the incremental inductance.
Z = sqrt(L/C)
tpd = sqrt(LC)
solving for Inductance
L = Z x tpd
For 50 ohm microstrip that would be 7.5 nH of inductance
per linear inch
of trace.
For 40 ohm microstrip = 6 nH/inch
For 30 ohm microstrip = 4.nH/inch
For 20 ohm microstrip = 3 nH/inch
You can use this, along with available publicly published
analytical
formulas for planes and vias to compute the total
inductance in the
power delivery system up to your ball pads, to determine
you power
system impedance vs. frequency.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Ryan Sequeira wrote:
Would like to understand the effects of supplying
power and ground to the
BGA by connecting
vias to the VCC/GND plains and traces outside the BGA
package.
Pros: Allows for larger vias outside the package.
Cons: Compromised noise performance through trace
length added to VCC/GND
trace length.
Is there something else that needs to be taken care
of....
The BGA device is a CPLD, IO=3.3V, Core=1.8V, Fmax > 180MHz, VCCO(3.3V) - 11
pins, VCC(1.8V) - 4 pins, GND - 15 pins
The device is a 132csBGA, 0.5mm pitch, 0.3mm pad. So
cannot afford to drop
the vias within the BGA area. Microvias would be too
expensive...
Ryan
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