[SI-LIST] Re: BGA vias outside the package

  • From: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • Date: Wed, 28 Jan 2009 13:43:30 -0500

Ryan

Use a 2D field solver to compute the impedance of the trace you'll use 
to connect the outer layer planes to the balls.  If microstrip, prop 
delay is approximately 150 ps/in.  Once you know your trace impedance 
you can compute the incremental inductance.

Z = sqrt(L/C)
tpd = sqrt(LC)

solving for Inductance
L = Z x tpd

For 50 ohm microstrip that would be 7.5 nH of inductance per linear inch 
of trace.
For 40 ohm microstrip = 6 nH/inch
For 30 ohm microstrip = 4.nH/inch
For 20 ohm microstrip = 3 nH/inch

You can use this, along with available publicly published analytical 
formulas for planes and vias to compute the total inductance in the 
power delivery system up to your ball pads, to determine you power 
system impedance vs. frequency.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Ryan Sequeira wrote:
> Would like to understand the effects of supplying power and ground to the
> BGA by connecting
> vias to the VCC/GND plains and traces outside the BGA package. 
>
> Pros: Allows for larger vias outside the package.
> Cons: Compromised noise performance through trace length added to VCC/GND
> trace length.
>
> Is there something else that needs to be taken care of....
>
> The BGA device is a CPLD, IO=3.3V, Core=1.8V, Fmax = 180MHz, VCCO(3.3V) - 11
> pins, VCC(1.8V) - 4 pins, GND - 15 pins
> The device is a 132csBGA, 0.5mm pitch, 0.3mm pad. So cannot afford to drop
> the vias within the BGA area. Microvias would be too expensive...
>
> Ryan
>
>
>
>
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