[SI-LIST] Re: 65 Ohm compact PCI impedance
- From: "Powell, Jon N" <jon.n.powell@xxxxxxxxx>
- To: "Sexton, Brian M. (US SSA)" <brian.m.sexton@xxxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 7 Jan 2009 11:13:39 -0800
I would be concerned about the measurement being Nominal instead of Min.
Jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Sexton, Brian M. (US SSA)
Sent: Wednesday, January 07, 2009 11:08 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] 65 Ohm compact PCI impedance
I'm designing a 5-slot, 66MHz cPCI backplane. We recently sent our
design out for fab, and the board house came back saying they were
measuring our compact PCI lines to be in the 57 ohm range. We have
.020" wide guard traces connecting the 'Z' and 'F' ground rows of
adjacent cPCI connectors. They claim this is the reason for the lower
impedance. The cPCI traces are about .005" wide and run about .026 from
the guard traces between connectors. They also run about .024" from
vias for the cPCI pins.
I'm curious if the guard traces have that much of an effect on the
impedance. I would think the via fields would play a significant role
in reducing the characteristic impedance as well. I'm wondering if the
cPCI standard assumes you take all these external factors into account,
or if they assume you shoot for 65 ohms but get slightly lower in
reality. I can't reduce the trace width since it's already at .0045 -
.005". Does anyone have any experience with this?
Also does anyone have experience running cPCI at an impedance that is
slightly below the 10% tolerance? 57 ohms is almost with in the 10%
window of [58.5 - 71.5].
Thanks for your help.
Brian
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