Posts for si-list, 04-2003

Browse: Last Month: 03-2003 Main Archive Page Next Month: 05-2003

» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] RMCEMC May Bonus Meeting -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Re: SDRAM bus termination -
» [SI-LIST] Re: Differential Signal at driver andintermediatepoints in xtk -
» [SI-LIST] Re: Differential Signal at driver and intermediate points in xtk -
» [SI-LIST] Re: Differential Signal at driver and intermediate points in xtk -
» [SI-LIST] Embedded inductors -
» [SI-LIST] Embedded capacitors -
» [SI-LIST] Differential Signal at driver and intermediate points in xtk -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: Test Loading Issues on Quad XTK -
» [SI-LIST] Re: Test Loading Issues on Quad XTK -
» [SI-LIST] Re: Shape factors for sheet resistance based estimations -
» [SI-LIST] Re: Test Loading Issues on Quad XTK -
» [SI-LIST] Re: DDR SDRAM Hints -
» [SI-LIST] Re: DDR SDRAM Help Request -
» [SI-LIST] DDR SDRAM Help Request -
» [SI-LIST] Shape factors for sheet resistance based estimations -
» [SI-LIST] Gold plating reference(s) -
» [SI-LIST] Re: Test Loading Issues on Quad XTK -
» [SI-LIST] Joined -
» [SI-LIST] Joined -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: Test Loading Issues on Quad XTK -
» [SI-LIST] Re: Where can get RGB signal's spec? -
» [SI-LIST] Test Loading Issues on Quad XTK -
» [SI-LIST] Re: transformer model -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] transformer model -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] FW: RS232 and RS422 -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] regarding noise in LVDS -
» [SI-LIST] test -
» [SI-LIST] Where can get RGB signal's spec? -
» [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. -
» [SI-LIST] RS232 and RS422 -
» [SI-LIST] Looking for Spectrum Analyzer info -
» [SI-LIST] Re: Simulation error -
» [SI-LIST] Re: digital vector -
» [SI-LIST] Re: Simulation error -
» [SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies -
» [SI-LIST] Re: Help: how to create IBIS model for a chip which containstwo dies -
» [SI-LIST] Simulation error -
» [SI-LIST] Re: digital vector -
» [SI-LIST] Help on Jtag Emulator connection for Debugging TI DSP -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: series term + fanout = noise? -
» [SI-LIST] Re: VNA Calibration for COAX Testing -
» [SI-LIST] Re: VNA Calibration for COAX Testing -
» [SI-LIST] Re: series term + fanout = noise? -
» [SI-LIST] series term + fanout = noise? -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] VNA Calibration for COAX Testing -
» [SI-LIST] spacing between via -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] Re: N-port model limitations in simulators -
» [SI-LIST] N-port model limitations in simulators -
» [SI-LIST] Re: Common Mode Return Loss Measurements -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Measuring Power/Gnd -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Re: Center of Mass of Transistors. -
» [SI-LIST] Re: Center of Mass of Transistors. -
» [SI-LIST] Re: Center of Mass of Transistors. -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Re: HSPICE 2003.03 W-element concern -
» [SI-LIST] Re: Common Mode Return Loss Measurements -
» [SI-LIST] Re: How to terminate the bi-directional buses? -
» [SI-LIST] How to terminate the bi-directional buses? -
» [SI-LIST] Validation of spiral inductors -
» [SI-LIST] Re: EMI--bare board vs. case -
» [SI-LIST] Re: EMI--bare board vs. case -
» [SI-LIST] Center of Mass of Transistors. -
» [SI-LIST] Re: Common Mode Return Loss Measurements -
» [SI-LIST] Re: Common Mode Return Loss Measurements -
» [SI-LIST] Re: Common Mode Return Loss Measurements -
» [SI-LIST] EMI--bare board vs. case -
» [SI-LIST] Common Mode Return Loss Measurements -
» [SI-LIST] Re: Electrical Modeling Consultants (Bay Area) -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Re: What's difference between 3.5mm and SMA? -
» [SI-LIST] test - please ignore -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Re: [Fwd: coax to PCB transition - return loss] -
» [SI-LIST] Electrical Modeling Consultants (Bay Area) -
» [SI-LIST] HSPICE 2003.03 W-element concern -
» [SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. -
» [SI-LIST] [Q] Usual trace length for 64bit-wide bus using 250Mbps HSTL -
» [SI-LIST] RS232 transmit and receive frequency -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Jobs Opening -
» [SI-LIST] Jobs Opening -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: Measuring Crosstalk -
» [SI-LIST] Re: Measuring Crosstalk -
» [SI-LIST] Signal Integrity Engineer Seeking Position -
» [SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies -
» [SI-LIST] Re: What's difference between 3.5mm and SMA? -
» [SI-LIST] Re: Help: how to create IBIS model for a chip which containstwo dies -
» [SI-LIST] EPEP Books -
» [SI-LIST] Re: IBIS Model VT Curve Length -
» [SI-LIST] Re: Measuring Crosstalk -
» [SI-LIST] SPI4.2 over cable -
» [SI-LIST] Re: What's difference between 3.5mm and SMA? -
» [SI-LIST] via resistance -
» [SI-LIST] Re: diff-pair -
» [SI-LIST] diff-pair -
» [SI-LIST] AD bus -
» [SI-LIST] right pulse shape test way -
» [SI-LIST] Re: What's difference between 3.5mm and SMA? -
» [SI-LIST] Re: What's difference between 3.5mm and SMA? -
» [SI-LIST] What's difference between 3.5mm and SMA? -
» [SI-LIST] IBIS Model VT Curve Length -
» [SI-LIST] Transceiver -
» [SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies -
» [SI-LIST] Seeking SI opportunities -
» [SI-LIST] Re: Spiral Inductor -
» [SI-LIST] Help: how to create IBIS model for a chip which contains two dies -
» [SI-LIST] Measuring Crosstalk -
» [SI-LIST] New Software Question -
» [SI-LIST] New Software -
» [SI-LIST] Re: Does ferrite rod affect inductance ? -
» [SI-LIST] Re: coax to PCB transition - return loss -
» [SI-LIST] coax to PCB transition - return loss -
» [SI-LIST] Re: Spiral Inductor -
» [SI-LIST] Re: Buffering 125MHz GMII signals -
» [SI-LIST] Test Message -
» [SI-LIST] high speed digital design decoupling question -
» [SI-LIST] Does ferrite rod affect inductance ? -
» [SI-LIST] pin type definition for Mentor Expedition -
» [SI-LIST] Re: Spiral Inductor -
» [SI-LIST] Re: Spiral Inductor -
» [SI-LIST] Re: Spiral Inductor -
» [SI-LIST] Re: Buffering 125MHz GMII signals -
» [SI-LIST] DIMM power consumption -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] Re: Buffering 125MHz GMII signals -
» [SI-LIST] Buffering 125MHz GMII signals -
» [SI-LIST] TV tuner chips -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Spiral Inductor -
» [SI-LIST] Re: SPI03 ADVANCE REGISTRATION DEADLINE AND PROGRAM -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] search for clock oscillator -
» [SI-LIST] Re: Power distribution -
» [SI-LIST] Re: Power distribution -
» [SI-LIST] Power distribution -
» [SI-LIST] Re: search for clock oscillator -
» [SI-LIST] search for clock oscillator -
» [SI-LIST] SPI03 ADVANCE REGISTRATION DEADLINE AND PROGRAM -
» [SI-LIST] SMII interface imped design -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] Question: Circuit representation of partially filled soleniod withinductors. -
» [SI-LIST] Re: Immersion gold -
» [SI-LIST] Immersion gold -
» [SI-LIST] Re: The return of nickel! -
» [SI-LIST] Re: The return of nickel! -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: The return of nickel! -
» [SI-LIST] Re: Buffer Delay -
» [SI-LIST] The return of nickel! -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: Series Termination Resistance -
» [SI-LIST] Re: Series Termination Resistance -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: TRST signal of JTAG I/F -
» [SI-LIST] FW: TRST signal of JTAG I/F -
» [SI-LIST] Re: SPICE model -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Series Termination Resistance -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: LVDS Termination -
» [SI-LIST] Re: Converting S-parameter to Inductance and Capacitance -
» [SI-LIST] Re: SPICE model -
» [SI-LIST] LVDS Termination -
» [SI-LIST] Backplane 'overaly' question -
» [SI-LIST] SPICE model -
» [SI-LIST] IS DEPT TESTING EMAIL Filtering -
» [SI-LIST] Twist ratio in a Cat 5 cable -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Converting S-para to L,C --Si list -
» [SI-LIST] Re: a clocking scheme question -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Buffer Delay -
» [SI-LIST] Re: Buffer Delay -
» [SI-LIST] Re: Buffer Delay -
» [SI-LIST] wats ferrite affection -
» [SI-LIST] Re: a clocking scheme question -
» [SI-LIST] Creating Cable Models in SPECCTRAquest -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] a clocking scheme question -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] unset [listname] vacation -
» [SI-LIST] Re: help -
» [SI-LIST] Re: TRST signal of JTAG I/F -
» [SI-LIST] help -
» [SI-LIST] Re: PECL vs LVDS -
» [SI-LIST] Re: Buffer Delay -
» [SI-LIST] Re: Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: Converting S-parameter to Inductance and Capacitance -
» [SI-LIST] Re: PECL vs LVDS -
» [SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX -
» [SI-LIST] Re: Converting S-parameter to Inductance and Capacitance -
» [SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX -
» [SI-LIST] Re: TRST signal of JTAG I/F -
» [SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? -
» [SI-LIST] Radiating Ceramic Bulk Capacitors -
» [SI-LIST] Re: TRST signal of JTAG I/F -
» [SI-LIST] Converting S-parameter to Inductance and Capacitance -
» [SI-LIST] TRST signal of JTAG I/F -
» [SI-LIST] Re: Coupled connector model -
» [SI-LIST] Test -
» [SI-LIST] Re: Question Concerning End Launch SMA connector. -
» [SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX -
» [SI-LIST] PECL vs LVDS -
» [SI-LIST] Re: Signal Integrity Manager Position at zzz -
» [SI-LIST] Re: serial loop-back causing clock error -
» [SI-LIST] Re: Difference in simulations results between Hspice and Pspice-ORCAD. -
» [SI-LIST] Difference in simulations results between Hspice and Pspice-ORCAD. -
» [SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX -
» [SI-LIST] serial loop-back causing clock error -
» [SI-LIST] Buffer Delay -
» [SI-LIST] Re: Question Concerning End Launch SMA connector. -
» [SI-LIST] Fw: Question Concerning End Launch SMA connector. -
» [SI-LIST] Re: Question Concerning End Launch SMA connector. -
» [SI-LIST] Re: Question Concerning End Launch SMA connector. -
» [SI-LIST] Question Concerning End Launch SMA connector. -
» [SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? -
» [SI-LIST] Standards -
» [SI-LIST] Re: different Vmeas for Rising/Falling -
» [SI-LIST] Re: different Vmeas for Rising/Falling -
» [SI-LIST] Re: different Vmeas for Rising/Falling -
» [SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? -
» [SI-LIST] Re: different Vmeas for Rising/Falling -
» [SI-LIST] Re: different Vmeas for Rising/Falling -
» [SI-LIST] different Vmeas for Rising/Falling -
» [SI-LIST] question concerning socket for SDRAM module - mechanical problem? -
» [SI-LIST] Cat 5 cable properties... -
» [SI-LIST] Re: measuring active-to-float time for PCI o/p buffer -
» [SI-LIST] Signal Integrity Manager Position at AMD -- Austin, TX -
» [SI-LIST] IBIS Modeling Tools -
» [SI-LIST] Re: stitched via shielding -
» [SI-LIST] Re: Material on SI in ASIC -
» [SI-LIST] Material on SI in ASIC -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] measuring active-to-float time for PCI o/p buffer -
» [SI-LIST] Re: [SI-LIST]Language conventions -
» [SI-LIST] PRBS generation for hspice -
» [SI-LIST] Maxwell matrixes in Hspice -
» [SI-LIST] Re: digital vector -
» [SI-LIST] Re: digital vector -
» [SI-LIST] Re: digital vector -
» [SI-LIST] digital vector -
» [SI-LIST] digital vector -
» [SI-LIST] Re: worst-case / best-case -
» [SI-LIST] worst-case / best-case -
» [SI-LIST] Re: R-T-F-M Re: Language conventions -
» [SI-LIST] Re: R-T-F-M Re: Language conventions -
» [SI-LIST] R-T-F-M Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Re: Language conventions -
» [SI-LIST] Language conventions -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] test,I am a new member -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] Re: Loss tangent calculation -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] Re: What Latium is -
» [SI-LIST] What Latium is -
» [SI-LIST] Re: loss tangent calculation -
» [SI-LIST] loss tangent calculation -
» [SI-LIST] Re: What is Latium Error?? -
» [SI-LIST] Re: What is Latium Error?? -
» [SI-LIST] Re: Coupled connector model -
» [SI-LIST] Re: Coupled connector model -
» [SI-LIST] Re: What is Latium Error?? -
» [SI-LIST] Re: What is Latium Error?? -
» [SI-LIST] Re: What is Latium Error?? -
» [SI-LIST] Re: Coupled connector model -
» [SI-LIST] What is Latium Error?? -
» [SI-LIST] Analyzing noise in chip packages -
» [SI-LIST] Coupled connector model -
» [SI-LIST] crosstalk-FastCap -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: IBIS, si simulators, modeling and other sourcesof correlation error -
» [SI-LIST] Re: IBIS, si simulators, modeling and other sourcesof correlation error -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error -
» [SI-LIST] Lookig for Signal Integrity Position -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: IEEE CPMT Society Phoenix Chapter - April 15 meeting announcement -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - April 15 meeting announcement -
» [SI-LIST] crosstalk-FastCap -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Re: Routing of 12 GHz diff pairs -
» [SI-LIST] Routing of 12 GHz diff pairs -
» [SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error -
» [SI-LIST] IBIS, si simulators, modeling and other sources of correlation error -
» [SI-LIST] Re: Signal Integrity Analysis Software -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Signal Integrity Analysis Software -
» [SI-LIST] Re: Signal Integrity Analysis Software -
» [SI-LIST] Re: Signal Integrity Analysis Software -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Signal Integrity Analysis Software -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: XTK model for I2C bus -
» [SI-LIST] Re: XTK model for I2C bus -
» [SI-LIST] XTK model for I2C bus -
» [SI-LIST] regarding standards Fcc etc., -