Posts for si-list, 03-2003

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» [SI-LIST] What software to design multilayer PCB -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Capacitor spice models which include dielectric losses -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: Skew and Jitter -
» [SI-LIST] Re: RC termination -
» [SI-LIST] Re: question regarding IBIS -
» [SI-LIST] question regarding IBIS -
» [SI-LIST] Re: Need some Info on Inductance.. -
» [SI-LIST] 1 analogic to 1 digital -
» [SI-LIST] SPI 2003 hotel reservation deadline -
» [SI-LIST] Re: Capacitor spice models which include dielectric losses -
» [SI-LIST] Re: RC termination -
» [SI-LIST] Re: a problem about PLL bypass -
» [SI-LIST] Re: a problem about PLL bypass -
» [SI-LIST] Re: a problem about PLL bypass -
» [SI-LIST] a problem about PLL bypass -
» [SI-LIST] Re: RC termination -
» [SI-LIST] RC termination -
» [SI-LIST] HyperLynx Lunch and Learn -
» [SI-LIST] Skew and Jitter -
» [SI-LIST] Star-rcxt: About parameter priority of mapping file -
» [SI-LIST] PCB manufactures control impedance report! -
» [SI-LIST] Re: PLL spectrum...[follow up] -
» [SI-LIST] Re: PLL spectrum... -
» [SI-LIST] PLL spectrum... -
» [SI-LIST] Re: Capacitor spice models which include dielectric losses -
» [SI-LIST] Re: SPI 4-2 question(s) -
» [SI-LIST] Capacitor spice models which include dielectric losses -
» [SI-LIST] Re: Need some Info on Inductance.. -
» [SI-LIST] Re: Need some Info on Inductance.. -
» [SI-LIST] SPI 4-2 question(s) -
» [SI-LIST] Need some Info on Inductance.. -
» [SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] Re: : TDR extender cable, 1m, Tektronix PN 012-1220-00 for my 11801B scope. -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] crosstalk-FastCap -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] PECL design: trace impedance -
» [SI-LIST] Re: laplace errors -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] EMI/EMC Engineer Job Opportunity -
» [SI-LIST] Re: Question about power delivery to silicon in a BGA package -
» [SI-LIST] FW: Ground clearance at connector vias -
» [SI-LIST] Question about power delivery to silicon in a BGA package -
» [SI-LIST] Re: Temperature variable in SI simulation -
» [SI-LIST] Re: stitched via shielding -
» [SI-LIST] stitched via shielding -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: (No Subject) -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: Temperature variable in SI simulation -
» [SI-LIST] Hspice vs Raphael -
» [SI-LIST] Re: (No Subject) -
» [SI-LIST] (No Subject) -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: laplace errors -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: Temperature variable in SI simulation -
» [SI-LIST] Re: HPSICE error -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: PC Parallel port to 3V3 -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] Re: Ground clearance at connector vias -
» [SI-LIST] laplace errors -
» [SI-LIST] Ground clearance at connector vias -
» [SI-LIST] Re: PC Parallel port to 3V3 -
» [SI-LIST] PC Parallel port to 3V3 -
» [SI-LIST] Re: Temperature variable in SI simulation -
» [SI-LIST] Temperature variable in SI simulation -
» [SI-LIST] HPSICE error -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: FW: How to add parellel terminator in IBIS -
» [SI-LIST] Re: Coax vs. Microstrip -
» [SI-LIST] Re: (no subject) -
» (no subject) -
» [SI-LIST] Re: Job Opportunity -
» [SI-LIST] Re: How to add parellel terminator in IBIS -
» [SI-LIST] Re: Job Opportunity -
» [SI-LIST] FW: How to add parellel terminator in IBIS -
» [SI-LIST] Re: Job Opportunity -
» [SI-LIST] Re: Job Opportunity -
» [SI-LIST] Re: How to add parellel terminator in IBIS -
» [SI-LIST] Re: Coax vs. Microstrip -
» [SI-LIST] Re: ask for comments on high frequency filter design -
» [SI-LIST] Re: Job Opportunity -
» [SI-LIST] Re: ask for comments on high frequency filter design -
» [SI-LIST] ACHIEVABLE TOLERANCE OF PCB TRACE WIDTH ? -
» [SI-LIST] How to add parellel terminator in IBIS -
» [SI-LIST] Re: ask for comments on high frequency filter design -
» [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Re: Coax vs. Microstrip -
» [SI-LIST] Re: Coax vs. Microstrip -
» [SI-LIST] ePlanner(Scratchpad)/XTK from Innoveda -
» [SI-LIST] Job Opportunity -
» [SI-LIST] ask for comments on high frequency filter design -
» [SI-LIST] Fwd: Comparison between Raphael and Hspice -
» [SI-LIST] How to Zigzag trace! -
» [SI-LIST] SI/EMC Job Openings -
» [SI-LIST] Re: PCI Edge connector -
» [SI-LIST] Re: PCI Edge connector -
» [SI-LIST] Re: Reflections for dummies -
» [SI-LIST] PCI Edge connector -
» [SI-LIST] hspice model for Giga Ethernet Tx/Rx -
» [SI-LIST] Re: Reflections for dummies -
» [SI-LIST] Reflections for dummies -
» [SI-LIST] Re: how to model connectors -
» [SI-LIST] Re: How to model Output buffer with feedback in IBIS? -
» [SI-LIST] Printed Resistors -
» [SI-LIST] how to model connectors -
» [SI-LIST] How to locate Lambda-Refine Mesh in HFSS? -
» [SI-LIST] Re: How to model Output buffer with feedback in IBIS? -
» [SI-LIST] How to model Output buffer with feedback in IBIS? -
» [SI-LIST] Ground setting in ADS of Agilent -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Flat Flex Cable Impedance - Measurement -
» [SI-LIST] Re: Doping effects. -
» [SI-LIST] Re: Doping effects. -
» [SI-LIST] Re: Question on Impedance Control -
» [SI-LIST] current rating of wirebonds -
» [SI-LIST] Re: Trace width and current capacity -
» [SI-LIST] Re: Doping effects. -
» [SI-LIST] Re: current rating of wirebonds -
» [SI-LIST] Re: Trace width and current capacity -
» [SI-LIST] which is the Best routing Topology -
» [SI-LIST] current rating of wirebonds -
» [SI-LIST] Re: Doping effects. -
» [SI-LIST] Looking for RF job in Canada -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Doping effects. -
» [SI-LIST] Doping effects. -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Question on Impedance Control -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] SI - VHDL -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Question on Impedance Control -
» [SI-LIST] Re: Question on Impedance Control -
» [SI-LIST] Question on Impedance Control -
» [SI-LIST] Re: Trace width and current capacity -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Flat Flex Cable Impedance -
» [SI-LIST] Re: Power plane thickness tolerance -
» [SI-LIST] Flat Flex Cable Impedance -
» [SI-LIST] Trace width and current capacity -
» [SI-LIST] Power plane thickness tolerance -
» [SI-LIST] Re: One question left!!!!! -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: One question left!!!!! -
» [SI-LIST] which is load and source treated -
» [SI-LIST] Re: Two requests -
» [SI-LIST] One question left!!!!! -
» [SI-LIST] Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Re: Two requests -
» [SI-LIST] Two requests -
» [SI-LIST] low noise oscillators -
» [SI-LIST] Re: S, ABCD and T parameters -
» [SI-LIST] Signal Integrity Contract -
» [SI-LIST] Re: SI conference/workshop in Germany? -
» [SI-LIST] Re: S, ABCD and T parameters -
» [SI-LIST] Re: SI conference/workshop in Germany? -
» [SI-LIST] SI conference/workshop in Germany? -
» [SI-LIST] Re: S, ABCD and T parameters -
» [SI-LIST] S, ABCD and T parameters -
» [SI-LIST] Re: Signal Integrity and Zeiger -
» [SI-LIST] Re: A presentation and more -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Re: Signal Integrity and Zeiger -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] [SI-LIST]Re: Problem with Ni plated transmission line -
» [SI-LIST] Re: Loss in HSPICE W Element -
» [SI-LIST] Re: Loss in HSPICE W Element -
» [SI-LIST] Measuring 1G+ signals -
» [SI-LIST] Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Carlsbad, CA High Speed Design for PCB Designers: Routing and Terminating High Speed -
» [SI-LIST] Re: Fw: Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Problem with Ni plated transmission line -
» [SI-LIST] Re: Problem with Ni plated transmission line -
» [SI-LIST] Re: Fw: Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Buried Vias and microvias -
» [SI-LIST] Re: Problem with Ni plated transmission line -
» [SI-LIST] Fw: Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Re: NEED PCB PRODUCED WITH BLIND & BURIED VIAS ? -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Re: Measuring 0.13micron CMOS devices -
» [SI-LIST] Fw: Problem with Ni plated transmission line -
» [SI-LIST] Re: Measuring 0.13micron CMOS devices -
» [SI-LIST] Measuring 0.13micron CMOS devices -
» [SI-LIST] Problem with Ni plated transmission line -
» [SI-LIST] Re: Loss in HSPICE W Element -
» [SI-LIST] Loss in HSPICE W Element -
» [SI-LIST] Buried Vias and microvias -
» [SI-LIST] Connectors and PECL terminations -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Re: Power Consumption of a bus -
» [SI-LIST] Power Consumption of a bus -
» [SI-LIST] DDR Module A13 Pin Location -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: A presentation and more -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] NEED PCB PRODUCED WITH BLIND & BURIED VIAS ? -
» [SI-LIST] Setting up Spectraquest to report capacitance for package design -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: [IS-LIST] Please Urgent -
» [SI-LIST] Re: A presentation and more -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Please Urgent -
» [SI-LIST] Available SI engineering position -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Please Urgent -
» [SI-LIST] Please Urgent -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: A presentation and more -
» [SI-LIST] A presentation and more -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Zo vs Zin -
» [SI-LIST] Zo vs Zin -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Series termination -
» [SI-LIST] Series termination -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) -
» [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Re: Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Single-ended S-para plot of 2 microstrip traces -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Re: Analog/Digital Gnd -
» [SI-LIST] Analog/Digital Gnd -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Bazooka balun verification. -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) -
» [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Sigrity seeks Applications Engineer -
» [SI-LIST] Re: contact ESD -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] contact ESD -
» [SI-LIST] Availability of IBIS models -
» [SI-LIST] Re: High speed diff. lines connector -
» [SI-LIST] High speed diff. lines connector -
» [SI-LIST] (No Subject) -
» [SI-LIST] (No Subject) -
» [SI-LIST] Re: Couple increased or decreased? (transmission line on silicon die) -
» [SI-LIST] IEEE Presentation download -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance -
» [SI-LIST] Crossing thick traces -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Couple increased or decreased? (transmission line on silicon die) -
» [SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance -
» [SI-LIST] Re: Length matching of source synchronous busses. -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Length matching of source synchronous busses. -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Needed Manager "SI" -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Re: Coupling THROUGH a plane? -
» [SI-LIST] Re: Coupling THROUGH a plane? -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Needed Manager "SI" -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Re: question about IBIS's V-T curve Scaling ? -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Instruments / Methods for measuring a cable's characteristic impedance -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Instruments / Methods for measuring a cable's chara cteristic impedance -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Instruments / Methods for measuring a cable'schara cteristic impedance -
» [SI-LIST] Re: how to calculate board area & stack -
» [SI-LIST] Re: is there any hspice to pspice convertor ? -
» [SI-LIST] Re: is there any hspice to pspice convertor ? -
» [SI-LIST] Re: is there any hspice to pspice convertor ? -
» [SI-LIST] Re: Inductance variation. -
» [SI-LIST] Re: Inductance variation. -
» [SI-LIST] Re: Inductance variation. -
» [SI-LIST] Re: Inductance variation. -
» [SI-LIST] Re: Inductance variation. -
» [SI-LIST] Inductance variation. -
» [SI-LIST] Instruments / Methods for measuring a cable's characteristic impedance -
» [SI-LIST] is there any hspice to pspice convertor ? -
» [SI-LIST] Modelling of Microwave Testing Microprobe (Cascade) -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] how to calculate board area & stack -
» [SI-LIST] Re: simulating Mos in series -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: simulating Mos in series -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Re: Loss Tangent of Solder Mask -
» [SI-LIST] Re: Controlled Impedance Coupon Design -
» [SI-LIST] Unlock the power of your backplane, LVDS tutorial (now with the link) -
» [SI-LIST] Re: Skin Effect Calculation -
» [SI-LIST] JEDEX Workshops on IBIS -
» [SI-LIST] Skin Effect Calculation -
» [SI-LIST] Re: Modeling a MUX/DEMUX? -
» [SI-LIST] Re: Modeling a MUX/DEMUX? -
» [SI-LIST] Re: Modeling a MUX/DEMUX? -
» [SI-LIST] Re: Modeling a MUX/DEMUX? -
» [SI-LIST] Modeling a MUX/DEMUX? -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Re: Differential signaling history -
» [SI-LIST] Differential signaling history -
» [SI-LIST] Unlock the power of your backplane, LVDS tutorial -
» [SI-LIST] measurement error -
» [SI-LIST] Re: NRZ signaling -
» [SI-LIST] Re: Hspice diff sim -
» [SI-LIST] Re: Hspice diff sim -
» [SI-LIST] Re: NRZ signaling -
» [SI-LIST] Re: NRZ signaling -
» [SI-LIST] Re: NRZ signaling -
» [SI-LIST] Re: NRZ signaling -
» [SI-LIST] Re: Decoupling a IC -
» [SI-LIST] NRZ signaling -
» [SI-LIST] Hot Swapping for -5V -
» [SI-LIST] Re: Plated through hole capacitance -
» [SI-LIST] Plated through hole capacitance -
» [SI-LIST] Re: 2.5GB/s data rate connector -
» [SI-LIST] Re: 2.5GB/s data rate connector -
» [SI-LIST] Re: 2.5GB/s data rate connector -
» [SI-LIST] Re: Canbus EMC/SI questions? -
» [SI-LIST] Re: 2.5GB/s data rate connector -
» [SI-LIST] 2.5GB/s data rate connector -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Meeting Announcement: Silicon Valley Chapter - IPC Designers Council (March 11) -
» [SI-LIST] Meeting Announcement: Silicon Valley Chapter - IPC Designers Council (March 11) -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Decoupling a IC -
» [SI-LIST] Canbus EMC/SI questions? -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] SI Guru -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Agenda (revised) , European IBIS Summit DATe 2003/Munich -
» [SI-LIST] Re: how to simulate with S parameters -
» [SI-LIST] Request some information about renting SPECCTRAQuest Products . -
» [SI-LIST] Re: 8b/10b program using MATLAB -