[SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies

Hi Lu,

I have had success using IBIS version 3.2 and the EBD (electrical board =
description  --  in section 8) for multiple die/single package products.

For my case, I had a CPU and two memory devices vertically stacked and =
connected together via a package substrate.  The bottom side of the =
package substrate had a ball array for attachment/connection to a PCB.  =
My on-chip topologies looked very similar to your depiction.

My final IBIS setup contained the following items:
1) IBIS model for the CPU with package parameters zeroed out
2) IBIS models for the memory devices (also with package params zeroed)
3) An EBD file that described: the package R, L, and C parameters for =
each trace; trace lengths; bond-wire RLC params from each die connection =
to the substrate; and pin-to-pin-to-pin-to-ball connection mapping =
between the stacked devices and the substrate ball.  Note, each mini =
topology points to the appropriate driver/receiver model in the IBIS =
files for the dies.
4) Readme.txt file summarizing how everything fits together for future =
users

The hardest part of this effort was generating accurate electrical =
models for the substrate traces.

A good example of this type of IBIS setup can be found on Micron's web =
page under SDRAM modules.  I learned from this list that several widely =
used SI simulators work fine with IBIS/EBD models.

Best of luck!

Rgds,

Dan

-----Original Message-----
From: Lu@xxxxxxxxxx [mailto:Lu@xxxxxxxxxx]
Sent: Wednesday, April 16, 2003 2:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Help: how to create IBIS model for a chip which
contains two dies



Hello Guys,

I am new to the IBIS model creation. I have some questions about how to
create IBIS model for a chip which contains two dies. especially in the
following case:

There is an I/O buffer in die 1, which connects to another I/O buffer in
die 2, then to the pin.

+--------------------------------*--------+
|                                |        |
|         +------------------+---+        |
|         |                  |            |
|         |                  |            |
|   +-----*--+        +------*----+       |
|   |        |        |           |       |
|   |        |        |           |       |
|   | die 1  |        |  die 2    |       |
|   |        |        |           |       |
|   +-----*--+        +------*----+       |
|                                         |
|                                         |
|                                         |
|              chip                       |
+-----------------------------------------+

1. How can I choose the model for this pin, say I already have models =
for
each I/O buffers?
2. Is R_pkg, L_pkg and C_pkg is sufficient to model the trace among 2 =
I/Os
and pin?
3. which IBIS version should I use: 2.1 or 3.2?

I'll appreciate if you give me any opinions or suggestions. Thanks.


*************************
 Lixin Lu
 IC CAD Specialist
 MOSAID Technologies Inc.
 11 Hines Road,
 Kanata, Ontario
 Canada K2K 2X1
 (613) 599 9539 ext 1638
*************************



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