[SI-LIST] Re: DDR SDRAM Help Request

Paul,

DDR SDRAM uses SSTL signaling and the standard is JEDEC Standard No 8-9,
also known as EIA/JESD8-9.  The DDR SDRAM specification standard is JESD79.
Both are downloadable from JEDEC website. The URLs are 

http://www.jedec.org/download/search/jesd8-9.pdf

http://www.jedec.org/download/search/JESD79R2.pdf


It depends on whether you are designing with DDR DIMMs or as embedded ICs.
There is lot of information on the Micron website
http://www.micron.com/products/toolbox.jsp?path=/DRAM/DDR+SDRAM

in their DDR Designer's Toolbox.  You can probably find some more additional
information on the other vendor's websites.  Most of this information
discusses on the DIMM based system design.  If you are designing embedded
system, then information is limited, but the system will be simpler to
design but simulation is highly recommended.

Hope this helps,
Prasad

-----Original Message-----
From: Paul Levin [mailto:levinpa@xxxxxxxxxxxxx]
Sent: Monday, April 28, 2003 3:13 PM
To: SI-List Reflector
Subject: [SI-LIST] DDR SDRAM Help Request



Dear All,

I've never worked on a DDR SDRAM system before. While
I have the manufacturer's data sheet, I am seeking
general references, especially a generic timing diagram
for write and read cycles. Is there some sort of
industry standard that governs these modules?

If anyone could send me reference(s) or point me to
them on the internet, it would be greatly appreciated.

Consultants, *please* do not write offering me your
services. Once armed with with the requested information,
I suspect that we can do this ourselves.

Thank you all for your assistance.

Regards,

Paul

-- 
Paul Levin
Senior Principal Engineer
Xyratex Storage Systems

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