[SI-LIST] Re: IBIS Model VT Curve Length
- From: "Todd Westerhoff" <twesterh@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 17 Apr 2003 10:09:05 -0400
Excellent question.
There is another alternative - if there is "dead time" in the V-T curves
before the output starts switching, you can remove it - AS LONG AS - you
remove the *same* amount of time from both sets of rising and falling V-T
curves (this is the IBIS model duty cycle discussion we had a ways back).
Removing dead time from the front of the curves may get you to the point
where the output switches fully within the data period you intend, which is
really where you want to be.
As to your options (and these are my personal opinions)...
1) Is probably your best bet, since that's how your buffer actually works.
Problem is, switching the output before the curve hits steady state can
cause abrupt discontinuities in the buffer's output behavior, which gets
ugly. But, the model will work correctly at slower speeds.
2) Is not a good idea, since you're actually deleting model information (and
you're also ensuring that the voltage the one edge settles at is different
from the voltage the other edge starts at, regardless of switching speed).
3) Means you're actually altering the switch rate of the buffer. In other
words, you're simulating something else.
In your shoes, I'd really be hoping that removing dead time from the front
of the curves would make things work. Without that, I'd try (1) and only
fall back to (3) if the simulations exhibited glitches I didn't believe (and
couldn't live with).
Hope that helps,
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"When did the choices get so hard, with so much more at stake?
Life gets mighty precious when there's less of it to waste"
- Bonnie Raitt, "Nick of Time"
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Moran, Brian P
Sent: Wednesday, April 16, 2003 8:23 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Model VT Curve Length
Hi Guys and Gals,
Just curious if any of you IBIS types out there have had to ponder the =
issue of trying to create IBIS models for buffers whose IBIS fixture =
generated VT curves do not fully switch in the minimum pulse width of =
your fastest intended stimulus, or more generally where the length of =
the VT curve is longer than Tp/2, where Tp=3D 1/Fmax. In such cases you =
can experience an issue some call "switching into an unfinished edge", =
which can create discontinuities in the output waveforms of some =
simulators. The right answer is probably to speed up the buffer, but in =
the mean time, I have 3 choices to weigh. 1) I can just leave the VT =
curves longer than the stimulus would normally dictate and let the =
simulator deal with it, 2) I could clip off the trailing edge of the VT =
curves, in which case they would not reach actual steady state level, or =
3) I can scale the VT curve's slope in order to fit the window. I guess =
I'm weighing 1 vs 3. I know scaling the VT will distort the model, which =
isn't good, but it is deterministic. The first option maintains the =
correctness of the model, but is less deterministic to my way of =
thinking, becasue I don't know how it effects various simulators. I'd be =
curious if anyone has been in this situation and done any type of =
analysis of the relative impact of either approach on simulation =
accuracy, or how various simulators react to the unfinished edge =
phenomenon. This is probably a philosophical rat hole, but I was hoping =
someone might have a piece of insight I had not thought of, or a =
workaround I had not considered. =20
Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@xxxxxxxxx
-----Original Message-----
From: Aaron Helleman [mailto:aaron.helleman@xxxxxxxxxxx]
Sent: Wednesday, April 16, 2003 2:25 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Measuring Crosstalk
What's the standard way to measure crosstalk in the lab? We have
experimentally determined that there is crosstalk on our PCB due
to traces being too close together for an xDSL system on the analog
side. We want to characterize the amount of crosstalk between two
'bad' ports vs. two 'good' ports
to determine if our respin will work properly in simulation.
The frequency band of interest is between DC and 1100 KHz, which seems
like it should not be succeptable to crosstalk very much, but we have
experimentally determined
that if we re-route the tracks of interest using rework wire we can make
the crosstalk go away.
Would a spectrum analyzer and a signal generator be the way to go, or
perhaps a network analyzer to check the rejection ratio?
Could we do this via simulation as well?
--
Aaron
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