[SI-LIST] Re: What is Latium Error??
- From: "Lori Lesnick" <loril@xxxxxxxxxxxxxxxxx>
- To: <binoshbc@xxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 3 Apr 2003 11:47:37 -0800
Hello Binosh,
It is definitely a design rule check error.
The error can apply to SI or cannot apply to SI. It depends on the type of
check you are running.
Under Tools/Verify Design
Did you check the LATIUM DESIGN VERIFICATION BOX?
OR
Under Tools/Verify Design/Clearance Then select setup
Did you check Latium Errors?
If you want to email me more information I will be happy to assist.
Or you can email your local representative for PowerPCB.
Mentor Graphics Support Net is also a good place to visit.
http://www.mentor.com/supportnet/
Best Regards,
Lori
Lori Lesnick
Sales Engineer
ECADware, LLC
1240 India Street, Suite 1403
San Diego, CA 92101
619.282.3500 Office
619.757.3501 Cell
619.282.3650 Fax
www.ecadware.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Binosh Balachandra
Sent: Thursday, April 03, 2003 5:05 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] What is Latium Error??
Hi SI gurus,
I am using POWERPCB & I came across a design verification called "LATIUM =
DESIGN VERIFICATION" Pls can anybody explain me what does this mean?? Is =
it something to do with SI?? =20
Hoping for a reply
Thanks in Advance
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