[SI-LIST] Seeking SI opportunities

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Dear Si-list members,

One of our si-list member and my ex-colleague is currently seeking =
opportunities in the signal integrity area. He has a Ph.D in EE with =
over 7 years of experience in this area. I am attaching
a partial copy of his resume. If any of you find any interest, please =
contact me for=20
further proceeding.=20


Thanks.

-bery





-- Attached file included as plaintext by Ecartis --
-- File: res.txt

EDUCATION   Ph.D. in Electrical Engineering    1996   

Areas of Specialization: Signal Integrity, Crosstalk, SSN, Power/Ground Noise 
and EMI Analysis of multi-Gigabit PCBs, Interconnects and Package Development 
of IC/FPGA devices, Cables and Connectors modeling and Multi-board system 
analysis, ISI and Jitter Analysis of Gigabit Serial Clock/Data link, 2D/3D 
Electromagnetic Modeling and Simulation. 
 
EXPERIENCE      
Lead Engineer (Signal Integrity)                        10/00 - Present
Fortune 500 Telcomm company 
* Responsible for managing all signal integrity efforts and leading the signal 
integrity team within the development Group.
* Evaluate and integrate various hardware CAE tools into the design 
environment. Interface with tool vendors to explore/upgrade tool features.
* Conduct pre-placement, pre- and post-layout signal integrity and crosstalk 
analysis of various application boards, backplanes and multi-board systems 
operating up to 3.125Gb/s. 
* Interface with IC vendors and Internal VLSI group to characterize IO buffers 
and develop tool specific (SPICE, IBIS, DML etc.) simulation models for ASICs, 
ICs, and FPGAs. Verify the accuracy of all models and build custom model 
libraries for SI/Timing analysis tools.
* Develop and maintain various floor planning and pre/post-layout analysis 
methodologies/scripts for PCB design tools and train and consult HW engineers 
with tools through seminar/workshop.
* Develop, model and characterize internal IC packages and verify external 
custom IC packages using Ansoft SpiceLink and HFSS tool suite.
* Perform lab measurements and correlate most simulation results with lab 
results using digital sampling oscilloscope, DCA, TDR, and VNA.
* Develop, characterize and correlate interconnect simulation models and design 
backplane/board stackup for multi-board 3.125 Gb/s serial links. 
* Characterize high-speed connectors from Teradyne, Molex, and Tyco using 
Ansofts HFSS and Spicelink tool suite and develop multi-line PEEC distributed 
models from Vendor data and convert the model into IBIS, Cadence DML and 
Mentors MMF format.
* Derive physical routing/placement constraints, develop termination schemes 
and optimized topologies, optimized stackup, and analyze timing budget and 
noise margin. 
* Extensively use Specctraquest, ICX, and XTK signal integrity simulation 
tools. Experienced with design database translation from Mentor Boardstation to 
Cadence Allegro and Innoveda XTK.

Senior Development Engineer (Signal Integrity)            02/97 - 09/00
Fortune 500 Networking company
* Evaluated and integrated various hardware CAE tools into the design 
environment. Interface with vendors to explore/upgrade tool features.
* Performed Pre- and Post-layout Signal Integrity and Timing analysis of 
various Router cards, Netserver cards, Network Interface cards, and Backplanes.
* Developed simulation models (from spice) for ICs, FPGAs and connectors, 
verify their accuracy and build custom model library for SI/Timing analysis 
tools.
* Developed various floorplaning and pre/post-layout analysis 
methodologies/scripts for PCB design tools and train and consult HW engineers 
with tools through seminar/workshop.

Design Engineer                                           02/96 - 01/97
Fortune 500 Networking company
* Developed and characterized and correlate simulation models (IBIS/SPICE) of 
I/O buffers for ICs and ASICs using HSPICE simulation.
* Designed and verified I/O circuit topologies based on various I/O signaling 
standard (LVTTL, LVCMOS, SSTL, HSTL etc.) . 
* Designed and verified various ASIC blocks including PCI bus interface models, 
FIFO models, SRAM and DRAM models and Controllers. Models are written in VHDL.
* Worked closely with Hardware Engineers and developed design 
scripts/methodologies (in C/perl/awk) for various IC synthesis and simulation 
tools.


COMPUTER/TOOL SKILLS                 
Software Languages    : C, C++, Parallel C (iPSC/860), Perl, Awk, FORTRAN.
Hardware Languages    : Spice, HSpice, VHDL, VeriLog, Familiar with Assembly.
Operating Systems     : UNIX (Solaris & HP), MSDOS, and Windows2000/NT.
Signal Integrity Tools: Spectraquest, Sigxplorer ,  ICX, XTK, QUIET, Hyperlynx, 
Eplanner, Avant! Hspice, Awaves, Specctra, Timing Analyzer, TAU, Power 
Integrity, Apsim.
Package Dev  Tools    : Ansoft SpiceLink, HFSS,  Innoveda XFX, XFX3D, Cadence 
APD.    
EM Modeling  Tools    : AutoCAD,  EMAP3D, Ansoft SpiceLink, HFSS,  Innoveda 
XFX, XFX3D.
PCB Layout  Tools     : Cadence Allegro, Orcad, Mentor Boardstation,            
                           
Other CAE Tools       : Viewdraw, Viewsim,  Board Architect, Modelsim,  XACT, 
MAXPLUS,    Mathematica, MathCAD, Matlab.
Measurement Tools     : Agilent 86100A DCA w/ TDR option, Agilent 8720ES VNA, 
DSO, Iconnect.

  


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