[SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies
- From: "Crain, Dan S" <dan.s.crain@xxxxxxxxx>
- To: <Lu@xxxxxxxxxx>
- Date: Thu, 17 Apr 2003 09:11:21 -0700
My pleasure Lixin. I am happy for the opportunity to give a little back =
to members of this terrific forum. Best of luck.
Rgds,
Dan
-----Original Message-----
From: Lu@xxxxxxxxxx [mailto:Lu@xxxxxxxxxx]
Sent: Thursday, April 17, 2003 8:33 AM
To: Crain, Dan S
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Help: how to create IBIS model for a chip
which contains two dies
Hi Dan,
Thanks a lot! your email is very helpful. I found some IBIS files from
intel which have same setup as you mentioned, maybe you create them:) =
I'll
have a look at the IBIS section about EBD, and ask the package company =
to
see if I may get the EBD file from them, otherwise, I need create it by
myself.
Again, thanks.
Lixin
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| | "Crain, Dan S" |
| | <dan.s.crain@inte|
| | l.com> |
| | Sent by: |
| | si-list-bounce@fr|
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| | |
| | |
| | 04/16/03 07:40 PM|
| | Please respond to|
| | dan.s.crain |
| | |
|---------+---------------------------->
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>------------------------------------------------------------------------=
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| =
|
| To: <Lu@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx> =
|
| cc: =
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| Subject: [SI-LIST] Re: Help: how to create IBIS model for a =
chip which contains two dies |
=
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Hi Lu,
I have had success using IBIS version 3.2 and the EBD (electrical board =
=3D
description -- in section 8) for multiple die/single package products.
For my case, I had a CPU and two memory devices vertically stacked and =
=3D
connected together via a package substrate. The bottom side of the =3D
package substrate had a ball array for attachment/connection to a PCB. =
=3D
My on-chip topologies looked very similar to your depiction.
My final IBIS setup contained the following items:
1) IBIS model for the CPU with package parameters zeroed out
2) IBIS models for the memory devices (also with package params zeroed)
3) An EBD file that described: the package R, L, and C parameters for =
=3D
each trace; trace lengths; bond-wire RLC params from each die connection =
=3D
to the substrate; and pin-to-pin-to-pin-to-ball connection mapping =3D
between the stacked devices and the substrate ball. Note, each mini =3D
topology points to the appropriate driver/receiver model in the IBIS =3D
files for the dies.
4) Readme.txt file summarizing how everything fits together for future =
=3D
users
The hardest part of this effort was generating accurate electrical =3D
models for the substrate traces.
A good example of this type of IBIS setup can be found on Micron's web =
=3D
page under SDRAM modules. I learned from this list that several widely =
=3D
used SI simulators work fine with IBIS/EBD models.
Best of luck!
Rgds,
Dan
-----Original Message-----
From: Lu@xxxxxxxxxx [mailto:Lu@xxxxxxxxxx]
Sent: Wednesday, April 16, 2003 2:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Help: how to create IBIS model for a chip which
contains two dies
Hello Guys,
I am new to the IBIS model creation. I have some questions about how to
create IBIS model for a chip which contains two dies. especially in the
following case:
There is an I/O buffer in die 1, which connects to another I/O buffer in
die 2, then to the pin.
+--------------------------------*--------+
| | |
| +------------------+---+ |
| | | |
| | | |
| +-----*--+ +------*----+ |
| | | | | |
| | | | | |
| | die 1 | | die 2 | |
| | | | | |
| +-----*--+ +------*----+ |
| |
| |
| |
| chip |
+-----------------------------------------+
1. How can I choose the model for this pin, say I already have models =
=3D
for
each I/O buffers?
2. Is R_pkg, L_pkg and C_pkg is sufficient to model the trace among 2 =
=3D
I/Os
and pin?
3. which IBIS version should I use: 2.1 or 3.2?
I'll appreciate if you give me any opinions or suggestions. Thanks.
*************************
Lixin Lu
IC CAD Specialist
MOSAID Technologies Inc.
11 Hines Road,
Kanata, Ontario
Canada K2K 2X1
(613) 599 9539 ext 1638
*************************
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