[SI-LIST] Re: worst-case / best-case
- From: Mike Mayer <mwmayer@xxxxxxx>
- To: "Si-List (E-mail)" <si-list@xxxxxxxxxxxxx>
- Date: 06 Apr 2003 09:51:26 -0500
It is based on the assumption that it is a CMOS part, and timing is the
limiting factor. So the worst case is the set of conditions that will
give the longest propagation delay, and best case the set of conditions
that will give the shortest propagation delay.
"Slow" and "fast" or "strong" and "weak" may be less ambiguous.
On Sun, 2003-04-06 at 08:06, Yoni Tzafrir wrote:
>
> hi,
> some of the spice models, are suppose to run in various conditions. the
> vendor of the models call those conditions:
> Worst Case - when specifying high temperature, and low Vdd voltages
> Best Case - when specifying low temperature, and high Vdd voltages
>
> can someone explain why those conditions are called Worst Case, or Best
> Case?
> Yonatan (Yoni) Tzafrir
> *Tel: (972) - 3 - 7552300 (T/L: 351)
> *Fax: (972) - 3 - 6177130
> *Mobile: (972) -54- 459469
> *E-mail: <mailto:yonitz@xxxxxxxxxxxxx>
>
>
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--
=============================================================================
Mike Mayer
mwmayer@xxxxxxx
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