[SI-LIST] Re: SDRAM bus termination

The SDRAM stuff will work fine in point to point config as long as the =
data bus is short.  Shouldn't be a concern even though SSTL specs =
specify a high-z state.  I have no knowledge of the FPGA side of your =
situation but as long as it doesn't use the DQS preamble/postamble to =
set up any data window timings you'll be fine.  You can't do the =
preamble/postamble with point to point.  I've seen point to point SDRAM =
and DDR DRAM on testers using FPGAs and point to point with no issues.  =
Without termination there WILL BE a charge up time for the data bus, 1 =
or two bits worth maybe, depends.  You'll see this represented as the =
high/low swing gradually rising in DC level over a couple of successive =
reads (or bits).  As long as you know this is happening it shouldn't be =
an issue.

Shane San Miguel=20
Product Engineer=20
Platform Memory Operations=20
Intel Corporation=20


=20

=20



-----Original Message-----
From: ganesancp [mailto:ganesancp@xxxxxxxxxxx]
Sent: Tuesday, April 29, 2003 9:33 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM bus termination



Hello SI experts,

I am designing a board with one SDR SDRAM and i want to connect this=20
SDRAM to a Xilinx Virtex-E FPGA in another board. SDRAM interface=20
will be working at 120MHz and there is no other component in the bus=20
(point-to-point).=20

Any termination suggested for the data bus and any other SI related=20
issues expected in this configuration?

Regards,
Ganesan

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