Posts for si-list, 08-2004

Browse: Last Month: 07-2004 Main Archive Page Next Month: 09-2004

» [SI-LIST] 90 degree bend -links -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Unsubscribe -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: 802.11g/b transmitter duty cycle -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: 90 degree bend -
» [SI-LIST] 90 degree bend -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: LVDS center tap capacitor termination -
» [SI-LIST] LVDS center tap capacitor termination -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Design guidelines -
» [SI-LIST] SGMII PHY Specification ? -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Misplaced Query, but guidance sought... -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: [Bulk] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Job Opportunity -
» [SI-LIST] HSPICE vs. Eldo -
» [SI-LIST] Job Opportunity -
» [SI-LIST] Re: issue in IBIS modelling of LVDS buffer -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: [Bulk] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: issue in IBIS modelling of LVDS buffer -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] The frontside groundplane -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Re: a puzzling question -
» [SI-LIST] Re: Decoupling for PLL -
» [SI-LIST] Decoupling for PLL -
» [SI-LIST] Re: issue in IBIS modelling of LVDS buffer -
» [SI-LIST] Re: issue in IBIS modelling of LVDS buffer -
» [SI-LIST] Re: a puzzling question -
» [SI-LIST] R: a puzzling question -
» [SI-LIST] Re: a puzzling question -
» [SI-LIST] a puzzling question -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors-thanks -
» [SI-LIST] Re: Queries regarding SGMII PHY-system level understanding -
» [SI-LIST] Queries regarding SGMII PHY-system level understanding -
» [SI-LIST] Alternates for PCB solders -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] issue in IBIS modelling of LVDS buffer -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: CPW -
» [SI-LIST] CPW -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Bypass vs Decoupling capacitors -
» [SI-LIST] Re: low repetation traces crossing splits -
» [SI-LIST] low repetation traces crossing splits -
» [SI-LIST] Bypass vs Decoupling capacitors -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Input impedance of Power trace -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: Input impedance of Power trace -
» [SI-LIST] Re: Input impedance of Power trace -
» [SI-LIST] Re: Query -
» [SI-LIST] Re: Input impedance of Power trace -
» [SI-LIST] Input impedance of Power trace -
» [SI-LIST] Internship Available -
» [SI-LIST] Job opening for EDA Application Engineer -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] INFO: Last call for IBIS Training in SanJose, CA and Austin, TX -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] Re: Mounting pad Design?? -
» [SI-LIST] Re: Query Regarding DQS line in DDR-SDRAM's -
» [SI-LIST] Mounting pad Design?? -
» [SI-LIST] Query Regarding DQS line in DDR-SDRAM's -
» [SI-LIST] Hi,all. Does anyone know why DDR address signal with compensation cap is better than without compensation cap? thank you! -
» [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] Re: SI work - part or full time endeavor -
» [SI-LIST] EPEP-2004 -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] Re: GTL,HSTL,SSTL -
» [SI-LIST] Re: OT: Swamped with Out of Office replies... -
» [SI-LIST] OT: Swamped with Out of Office replies... -
» [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] GTL,HSTL,SSTL -
» [SI-LIST] Re: FW: Power plane / VCC plane as reference for differential -
» [SI-LIST] Re: FW: Power plane / VCC plane as reference for differential -
» [SI-LIST] Re: FW: Power plane / VCC plane as reference for differential -
» [SI-LIST] Re: SI work - part or full time endeavor -
» [SI-LIST] Ferrite for USB 2.0 Connector -
» [SI-LIST] Re: SI work - part or full time endeavor -
» [SI-LIST] Re: SI work - part or full time endeavor -
» [SI-LIST] SI work - part or full time endeavor -
» [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] Re: Connection to cable shields -
» [SI-LIST] Re: FW: Power plane / VCC plane as reference for differential -
» [SI-LIST] HELP -
» [SI-LIST] FW: Power plane / VCC plane as reference for differential -
» [SI-LIST] Re: Adapting the Metallic Transmission (UTP modelling) Part 3 (mistake in part 2) -
» [SI-LIST] Re: Query (2) -
» [SI-LIST] Re: Query -
» [SI-LIST] Re: Query -
» [SI-LIST] Re: Quantic-EMC -
» [SI-LIST] Re: Connection to cable shields -
» [SI-LIST] Re: Connection to cable shields -
» [SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] Re: Power plane / VCC plane as reference for differential microstrips -
» [SI-LIST] Power plane / VCC plane as reference for differencial microstrips -
» [SI-LIST] Re: Connection to cable shields -
» [SI-LIST] Re: Query -
» [SI-LIST] Query -
» [SI-LIST] Quantic-EMC -
» [SI-LIST] Re: Error analysis -
» [SI-LIST] Re: Connection to cable shields -
» [SI-LIST] Connection to cable shields -
» [SI-LIST] Anyone else receiving these messages when posting?? -
» [SI-LIST] Re: know a 30 layer PCB manufacturer? -
» [SI-LIST] Re: know a 30 layer PCB manufacturer? -
» [SI-LIST] Re: Ferrite Bead- Download available. -
» [SI-LIST] Re: Ferrite Bead -
» [SI-LIST] know a 30 layer PCB manufacturer? -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: Ferrite Bead -
» [SI-LIST] Ferrite Bead -
» [SI-LIST] Error analysis -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Course on Signal Integrity at San Jose State University - Reminder -
» [SI-LIST] pci express links -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Next UCB High Speed Class in Redwood City -
» [SI-LIST] Re: PCIX Clock routing and connector -
» [SI-LIST] pci express links -
» [SI-LIST] Re: IC package -
» [SI-LIST] allegro constraints export -
» [SI-LIST] allegro constraints export -
» [SI-LIST] SI Position Open -
» [SI-LIST] RMCEMC Career Ops page updated -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: PCIX Clock routing and connector -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Relationship between conductor and modal quantities of coupled transmission lines -
» [SI-LIST] R matrix of coupled transmission lines -
» [SI-LIST] Re: PCIX Clock routing and connector -
» [SI-LIST] PCIX Clock routing and connector -
» [SI-LIST] Re: Max & min parallelism -
» [SI-LIST] Re: IC package -
» [SI-LIST] HFSS literature -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: Pulse Generator -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: power-up sequencing -
» [SI-LIST] Re: power-up sequencing -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: Digital IF Receiver -
» [SI-LIST] Re: power-up sequencing -
» [SI-LIST] power-up sequencing -
» [SI-LIST] Digital IF Receiver -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: IC package -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] IC package -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Pulse Generator -
» [SI-LIST] in the IBIS models -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] Re: routing of DDR clock signals -
» [SI-LIST] routing of DDR clock signals -
» [SI-LIST] Re: Autorouter -
» [SI-LIST] Re: Autorouter -
» [SI-LIST] Autorouter -
» [SI-LIST] Re: FR4 PCB material thermal study -
» [SI-LIST] FR4 PCB material thermal study -
» [SI-LIST] Re: Regarding rising waveforms in the IBIS models -
» [SI-LIST] Regarding rising waveforms in the IBIS models -
» [SI-LIST] Re: HyperLynx Technical Marketing Engineer -
» [SI-LIST] Re: Metallic Transmission (UTP modelling) -
» [SI-LIST] Re: Metallic Transmission (UTP modelling) -
» [SI-LIST] Re: Metallic Transmission (UTP modelling) -
» [SI-LIST] Metallic Transmission (UTP modelling) -
» [SI-LIST] Re: what's the difference between the HSTL and SSTL_2 -
» [SI-LIST] Bus Analysers/adaptor cards and active probing -
» [SI-LIST] Re: what's the difference between the HSTL and SSTL_2 -
» [SI-LIST] what's the difference between the HSTL and SSTL_2 -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - Aug 17 meeting announcement -
» [SI-LIST] Open Position for Signal Intergity Engineer, Staff -
» [SI-LIST] RMCEMC July presentation download available -
» [SI-LIST] RMCEMC presentation now in pdf -
» [SI-LIST] Re: EMI Containment -
» [SI-LIST] Re: EMI Containment -
» [SI-LIST] RMCEMC Career ops update #2 -
» [SI-LIST] To develope SPICE model for IBIS model with Submodel description -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] RMCEMC Career Ops page updated -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: EMI Containment third try is the charm -
» [SI-LIST] Re: EMI Containment -
» [SI-LIST] Re: EMI Containment -
» [SI-LIST] Re: Transmitter for DDR1 controller DQ -
» [SI-LIST] Re: Which noise source is critial? -
» [SI-LIST] Re: EMI Containment -
» [SI-LIST] EMI Containment -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: The driver model of oscillator -
» [SI-LIST] The driver model of oscillator -
» [SI-LIST] Re: Which noise source is critial? -
» [SI-LIST] Re: IBIS model endpoints mismatch errors -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: Main attenuation effect of long cables -
» [SI-LIST] Re: IBIS model endpoints mismatch errors -
» [SI-LIST] Transmitter for DDR1 controller DQ -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Which noise source is critial? -
» [SI-LIST] Re: Design guidelines -
» [SI-LIST] Re: Design guidelines -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Design guidelines -
» [SI-LIST] Re: Main attenuation effect of long cables -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Main attenuation effect of long cables -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Re: Internal Inductance -
» [SI-LIST] Internal Inductance -
» [SI-LIST] Re: IBIS model endpoints mismatch errors -
» [SI-LIST] IBIS model endpoints mismatch errors -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Equations for creating twisted pair transmission lines? -
» [SI-LIST] Re: Equations for creating twisted pair transmission lines? -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Opening for Signal Integrity -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Equations for creating twisted pair transmission lines? -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] HyperLynx Technical Marketing Engineer -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Re: Sr. Signal Integrity Engineer opportunity -
» [SI-LIST] Re: Sr. Signal Integrity Engineer opportunity -
» [SI-LIST] Re: Measurement peaks of current. -
» [SI-LIST] Measurement peaks of current. -
» [SI-LIST] Re: Equations for creating twisted pair transmission lines? -
» [SI-LIST] Re: Equations for creating twisted pair transmission lines? -
» [SI-LIST] Equations for creating twisted pair transmission lines? -
» [SI-LIST] SI Engineer Positions at EMC Corporation, Hopkinton, MA -
» [SI-LIST] Fairchild HSPICE models -
» [SI-LIST] Wi-Fi EMI -
» [SI-LIST] INFO: IBIS and Simulation Technologies Training is available in San Jose, CA and Austin, TX -
» [SI-LIST] ECL IBIS Models! -
» [SI-LIST] Max & min parallelism -
» [SI-LIST] Re: about XAUI error -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Yet another ASCII Schematic program -