[SI-LIST] a puzzling question
- From: "suxianxian" <suxianxian@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 26 Aug 2004 11:03:53 -0000
I have a PCB board stackup as below
top layer
S2
S3
S4
S5
GND
VCC
S6
There is a 80M CLOCK on top layer, the clock trace is 4cm.The
thinkness of my board is 1.7mm .I do not know what the clock signal
will behave like.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
