[SI-LIST] Re: Power plane / VCC plane as reference for differencial microstrips
- From: "Niki Steenkamp" <niki@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 23 Aug 2004 14:46:07 +0200
Hi,
Thanks Steve, Chris and list members for the detailed answers. Chris,
unfortuantely I am the "layout dude" as well! ;-) I have basically =
gotton
rid of the split in the reference plane, but I have to use the VCC plane =
as a
return plane for some of the LVDS signals - I cannot use ground on both =
sides
of the board. I have tried use ground for the higher speed links, =
though.
As far as I understand there should be no real issue with using VCC as a
reference plane? I have placed a number of decoupling caps around the =
LVDS
IC's to provide a low impedance path between VCC and ground.
I have another question (of a more theoretical nature): If you look at =
a
differential signal, then the ground connection is only really needed to
carry the even mode currents since odd mode currents cancel out. So if =
you
ignore the even mode currents (lets say we have perfectly balanced =
drivers),
then you do not need a reference plane for return current. With a =
microstrip
on a PCB, the reference plane is however rerquired to get the impedance =
right
- the net current in the reference plane is however 0. Is this sort of
right? Would you still be able to get a 100ohm differential impedance =
if you
did not have a reference plane (say with a single layer PCB)? I would =
guess
that it is possible, but you would have to place the traces extremely =
close
together to get enough coupling. =20
Thanks!
Niki
=20
> -----Original Message-----
> From: steve weir [mailto:weirsp@xxxxxxxxxx]
> Sent: Friday 20 August 2004 10:58
> To: Niki Steenkamp; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Power plane / VCC plane as reference for
> differencial microstrips
>=20
>=20
> Niki, in a perfect world, the return current from each half of the=20
> differential pair is equal and opposite. This results in a=20
> net transverse=20
> current between the pairs in the return. If you had a split=20
> that is small=20
> compared to your signal content, then your description is fairly=20
> reasonable, under the assumption of perfectly balanced signaling.
>=20
> Now for the problems:
>=20
> Even without the split, the common mode signal content is=20
> going to excite=20
> the resonant cavity formed by your Vcc and ground planes. =20
> That's some=20
> pretty high frequency stuff, ( 600Mbps =3D 1.6ns / cell about=20
> 100-200ps Tr =3D=20
> 1.5-3GHz knee ), so this is an invitation to expensive EMC=20
> fixes, like a=20
> bullet proof case, or thin dielectrics. If your VCC islands=20
> are large,=20
> even thin dielectrics will be of limited help due to the=20
> board 1/2 wave=20
> resonances.
>=20
> With the plane splits, your CM has to find a new path, that=20
> is generally=20
> going to be through the plane to ground capacitance of each=20
> island. At the=20
> same time, the DM coupling in the region of the split will=20
> jump up, and you=20
> will have an impedance discontinuity.
>=20
> If you can avoid the topology you describe and reference the=20
> LVDS to only=20
> ground, your life will be easier. If not, you have a job in=20
> front of you=20
> that calls for modelling. If you are going to try to wing=20
> it, get some=20
> seriously low inductance capacitors to bridge the planes. =20
> Either X2Y, or=20
> IDC. are the best choices. However, you need to realize that=20
> the mounted=20
> inductance of those devices is going to still present a substantial=20
> impedance bump for signals with 100ps rise times. This thing=20
> is going to=20
> want to radiate.
>=20
> Steve.
> At 10:27 AM 8/20/2004 +0200, Niki Steenkamp wrote:
> >Hi,
> >
> >I have a six layer board that contains LVDS (up to 600mbps)=20
> traces on =3D
> >both
> >outer layers. The top layer uses the solid ground plane=20
> beneath it as
> >reference plane, while the bottom layer uses the split VCC plane as a
> >reference plane. I am worried about the bottom LVDS layer=20
> since the =3D
> >LVDS
> >traces have to run over two different VCC planes. If the=20
> transmission =3D
> >lines
> >where single ended (as opposed to differential), I would=20
> have had to =3D
> >make
> >sure the there is a low impedance path for the return=20
> current to cross =3D
> >from
> >the one VCC plane to the other (using decoupling caps close to the =
=3D
> >crossover
> >point, for instance), but since I am using differential signalling, =
=3D
> >there
> >should be (in theory at least) no net return current. The (equal and
> >opposite) return currents below each microstrip would simply=20
> "loop back" =3D
> >when
> >they reached the break in the reference plane and a new=20
> return current =3D
> >loop
> >will be created in the next plane. Am I understanding this=20
> correctly? =3D
> >I can
> >think of two real-world complications: the one is the finite=20
> break width
> >(where there is no reference plane, except the ground plane=20
> which is a =3D
> >lot
> >further away). The other is the imbalance in the LVDS=20
> drivers, making =3D
> >the
> >signal not perfrectly differential. I do not really have a=20
> feeling for =3D
> >this,
> >is it something to worry about? Can I expect a signicant=20
> reduction in =3D
> >signal
> >quality?
> >
> >I am unfortunately only a lowly digital design engineer, so my =3D
> >understanding
> >of the high frequency aspects are, well, limited at best! =20
> Any feedback =3D
> >from
> >the pros would be welcome!
> >
> >Regards,
> >Niki
> >=3D20
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>=20
>=20
>=20
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