[SI-LIST] SGMII PHY Specification ?
- From: Gunjan Mandal <gunjan_mandal@xxxxxxxxx>
- To: gunjan_mandal@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sun, 29 Aug 2004 21:31:05 -0700 (PDT)
HI,
This is regarding SGMII PHY again.
Is there any Specification for input
setuptime(minimum) for SGMII PHY since data has to be
latched by using clock. At the Tx end the Clock is
placed at the middle of data. So due to the noise and
jitter the alignment of clock-data will change at Rx
end which may violate setup/hold time at the Rx end.
I have not seenany such spec. If anyone knows please
help me.
With regards,
Gunjan
--- Gunjan Mandal <gunjan_mandal@xxxxxxxxx> wrote:
> Hi,
> I am writing e-mail regarding the system level
> understanding of SGMII PHY.
>
> I am doing the design of LVDS RX to be used for
> SGMII
> PHY.
> Could any one please answers my following queries:
>
> 1)Can there be any difference in differential
> voltage
> levels (VID) for clock and the data signals at the
> RX
> end provided they are coming from similar kind of
> transmitter (@ 1.3 GB/S)?
> If it is there can it be like this :
> Clock-VID=100mv
> Data-VID=400mv
> What is the system level scenario?
>
> 2) Can there be situation where the clock signal is
> having common mode of 2.2v and the data signal is
> having common mode of 0.2v?
>
> As per the IEEE spec the common variation comes due
> to
> the Ground potential difference between Tx and Rx.
> So, it should be same for data and clock as they are
> coming from same chip.
>
> How much the Common mode can differ between data
> and
> clock due to noise?
>
> I will look forward for the answers.
> With regards,
> Gunjan
>
>
>
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