[SI-LIST] Re: Decoupling for PLL
- From: steve weir <weirsp@xxxxxxxxxx>
- To: istvan.novak@xxxxxxxxxxxxxxxx, <leeritchey@xxxxxxxxxxxxx>, "zhangkun 29902" <zhang_kun@xxxxxxxxxx>
- Date: Sun, 29 Aug 2004 20:06:27 -0700
All, while Lee makes a good point that a well designed power system is a
critical system design requirement, my experience is closer to Istvan's on
this. Mfg's who give us scant hard information on power system
requirements generally do even worse when it comes to PLLs. I would like
to paraphrase Lee's comments as holding Vcc rail noise as: "Holding Vcc
noise to a 'low level' up to a few MHz obviates the need for separate
low-frequency power filtering to PLLs". A well behaved main power supply
up past the first few harmonics of the VRM switching voltage should
eliminate the need for a low frequency cut-off decoupling filter. However,
it won't necessarily eliminate the need for it.
A point that I think is worth mentioning is SSO. When the PLL power pin is
tied directly tot he planes, the PLL power pin becomes part of the signal
image return path, unnecessarily imposing voltage drops across the PLL
internal power distribution to SSO induced noise currents. Whether a given
PLL can tolerate those currents or not, is chip design specific. A
decoupling filter with a high series impedance blocks those currents. But
now, if we have a "suitably quiet" Vcc up into the low MHz, the filter
cut-off frequency can be similarly high, and the design can be very compact.
So, how much noise at what frequency can a given PLL tolerate? Wouldn't it
be nice if the chip mfgs told us?
Steve.
At 06:26 PM 8/29/2004 -0400, Istvan NOVAK wrote:
>Lee,
>
>I fully agree that the first line of defence is to create a
>quiet main supply rail for EMI and power quality reasons.
>Secondly, it would be very good to have more data
>from chip makers in terms of how much noise the chip's
>PLL supply pin can live with.
>
>The only extra consideration, which sometimes will result in a
>different optimum for a main supply rail versus PLL input design,
>namely a separate filter for the PLL analog pin, is when the
>system considerations end up with significantly different noise
>requirements for the main supply rail versus the PLL supply pin.
>It is not uncommon to have smain supply rails in high-speed
>systems, where you can easily live with 100mV noise or more.
>And there are PLLs where the recommended noise on the supply
>pin may be 10mV or less. You may say: use a different chip,
>where the PLL can live with more noise on the supply pin; and this
>is the way if there is a choice; sometimes, however, the designer
>will find no alternative chips. Frequency range considerations
>may also call for separate filtering. On a differential signaling
>system, a common-mode noise contents below a MHz may
>be tolerable up to a couple of hundred mV magnitude,
>but the PLL's low-frequency bandwidth is the most sensitive
>where it can pick up noise and increase jitter.
>
>Regards,
>Istvan
>
>
>----- Original Message -----
>From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
>To: "zhangkun 29902" <zhang_kun@xxxxxxxxxx>; "Istvan Novak"
><istvan.novak@xxxxxxxxxxxxxxxx>
>Cc: <a.ingraham@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Sunday, August 29, 2004 5:08 PM
>Subject: [SI-LIST] Re: Decoupling for PLL
>
>
> > All of this discussion around how to isolate PLLs from Vdd noise speak to
>a
> > symptom, namely, too much noise on Vdd.
> >
> > True, it is possible to add all manner of networks such as have been
> > discussed over the last few days, but these still only treat the symptom.
> >
> > It is a far better strategy to do a good job designing the power subsystem
> > so that ripple is held to a minimum. This is necessary to satisfy noise
> > budgets and to help make passing EMI tests easier anyway.
> >
> > The reason for these networks in the first place is that manufacturer's
> > applications notes did not and still do not properly advise a user on how
> > to design a good power subsystem. Once this is understood, and it isn't
> > such a tough topic, ripple will be well within the tolerances of well
> > designed PLLs.
> >
> > To support these statements, log onto www.procket.com. You will see a
> > terabit router that has hundreds of PLLs in it as well as 5000+ 2.4 GB/S
> > serial links. All of the PLLs are connected directly into the power plane
> > from which they draw power. There are no ferrite beads or other networks
> > in their power leads.
> >
> > All that was necessary was to design the decoupling, including plane
> > capacitance, such that ripple was less than 20 millivolts to make them all
> > happy.
> >
> > It would be far better if advice on how to achieve a maximum ripple
> > amplitude were given in applications notes along with how much ripple a
>PLL
> > can tolerate. This would allow predictable designs to be done.
> >
> > Among the reasons not to use ferrite beads in this manner are: they add
> > extra components and they carry the risk of presenting the PLL with a high
> > impedance source of power potentially making the PLL more unstable rather
> > that more stable.
> >
> > In almost all cases I have seen, ferrite beads are band aids for designs
> > and problems that are not well understood and carry the risk of making
> > designs worse rather than better. When things were slower, the tended to
> > do no harm, because the ICs involved were slow enough that the degradation
> > in power supply impedance didn't much matter. That is no longer true.
> >
> > Lee W. Ritchey
> > Speeding Edge
> > P. O. Box 2194
> > Glen Ellen, CA 95442
> > Phone- 707-568-3983
> > FAX- 707-568-3504
> >
> > I just used the energy it took to be angry to write some blues.
> > Count Basie
> >
> >
> > > [Original Message]
> > > From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
> > > To: Istvan NOVAK <istvan.novak@xxxxxxxxxxxxxxxx>
> > > Cc: <a.ingraham@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > > Date: 8/30/2004 12:00:11 AM
> > > Subject: [SI-LIST] Re: Decoupling for PLL
> > >
> > > Istvan
> > >
> > > The input of PLL is clock of 77MHz and the output is clock of 622MHz. I
> > measure the noise at 77MHz, 154MHz, 231MHz, ... , 622MHz, and so on.
> > >
> > > We have found that there is some problem below 250KHz. My solution is to
> > use some beads of high impedance in low frequency domain. I have not check
> > the result.
> > >
> > > Best Regards
> > >
> > > Zhangkun
> > > 2004.8.29
> > >
> > > ----- Original Message -----
> > > From: Istvan NOVAK <istvan.novak@xxxxxxxxxxxxxxxx>
> > > Date: Sunday, August 29, 2004 9:23 pm
> > > Subject: Re: [SI-LIST] Re: Decoupling for PLL
> > >
> > > > Zhangkun,
> > > >
> > > > When you say "harmonic frequency", do you mean the
> > > > output frequency of PLL? Most of the time the output
> > > > frequency is much higher than the PLL's filter bandwidth,
> > > > which is usually in the hundreds of kHz. PLLs tend to
> > > > be sensitive to noise on their analog supply pin at or
> > > > below the filter bandwidth. Have you also compared the
> > > > noise below 1MHz?
> > > >
> > > > Regards,
> > > > Istvan
> > > >
> > > >
> > > > ----- Original Message -----
> > > > From: "zhangkun 29902" <zhang_kun@xxxxxxxxxx>
> > > > To: <a.ingraham@xxxxxxxx>
> > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > Sent: Sunday, August 29, 2004 5:34 AM
> > > > Subject: [SI-LIST] Re: Decoupling for PLL
> > > >
> > > >
> > > > > Andy
> > > > >
> > > > > I use spectrum analyzer to measure the power ground noise in
> > > > frequencydomain. At almost all the harmonic frequency, the
> > > > amplitude with 0 ohm
> > > > resistor is less of 3db than that with bead.
> > > > >
> > > > > The pre-filter power is of plane pair.
> > > > >
> > > > > Best Regards
> > > > >
> > > > > Zhangkun
> > > > > 2004.8.29
> > > > >
> > > > > ----- Original Message -----
> > > > > From: Andrew Ingraham <a.ingraham@xxxxxxxx>
> > > > > Date: Saturday, August 28, 2004 9:48 pm
> > > > > Subject: [SI-LIST] Re: Decoupling for PLL
> > > > >
> > > > > > Zhangkun,
> > > > > >
> > > > > > Some PLLs can be very sensitive to tiny amounts of noise. They
> > > > > > are, after
> > > > > > all, analog devices.
> > > > > >
> > > > > > When you say the noise difference is only 3dB, (1) that might be
> > > > > > just enough
> > > > > > of a difference to cause a problem, if your circuits were just on
> > > > > > the edge
> > > > > > of misbehaving; and (2) if you are measuring and comparing
> > > > > > broadband noise,
> > > > > > it is a meaningless comparison. The PLL is particularly sensitive
> > > > > > to noise
> > > > > > at particular frequencies, and you may need to look specifically
> > > > > > for those
> > > > > > frequencies. A broadband noise measurement could mask the
> > > > > > frequencies that
> > > > > > are causing the problem. Even a spectrum analyzer might, if you
> > > > > > don't know
> > > > > > what frequencies to look for.
> > > > > >
> > > > > > Another thought: does connecting the instruments to measure
> > > > the noise,
> > > > > > significantly affect the circuit? Maybe simply connecting probes
> > > > > > reducesthe noise enough to stop that PLL from misbehaving (while
> > > > > > the other two PLLs
> > > > > > continue to misbehave).
> > > > > >
> > > > > > How clean is the pre-filtered power? Is it a plane?
> > > > > >
> > > > > > Is there anything else of an analog nature on this board?
> > > > > >
> > > > > > Regards,
> > > > > > Andy
> > > > > >
> > > > > >
> > > >
> > > >
> > > >
> > >
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