[SI-LIST] Re: Decoupling for PLL
- From: "Nguyen, Mike" <Mike_Nguyen@xxxxxxxxxxxxxxxxx>
- To: <weirsp@xxxxxxxxxx>, "Ray Anderson" <reanderson@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 26 Aug 2004 12:25:19 -0700
Thank you, Ray. I simulated this ferrite bead-ceramic cap low-pass
filter
And saw a peak at the 3db point. This peak is around 8db. The 3db point
is
Around 10Khz. Shall I say this peak is harmless because my board does
not have
Any frequency near 10Khz. My DC-DC frequencies are from 100Kz-2Mhz.
I also simulated with a Tant. Cap instead of cer cap and the peak is
gone. The draw back is the 3db point now at 100Kz.
Adding an extra small resistor is good but cost extra parts. If the peak
happens at a non-existing frequency, why do I care?
Mike N.
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
=3D
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Thursday, August 26, 2004 12:05 PM
To: Ray Anderson; si-list@xxxxxxxxxxxxx
Cc: zhang_kun@xxxxxxxxxx
Subject: [SI-LIST] Re: Decoupling for PLL
Ray, zhang_kun, any linear filter book will show you your=20
options. Basically, you should start with the required impedance of the
filter at DC, use that to determine your resistor, and then derive L and
C=20
based on the cut-off frequency required. To contain the ringing, set
the=20
damping coefficient to a reasonably high value. Circuit 3A used to be
very=20
popular with voltage mode switching power supplies.
Steve.
At 11:26 AM 8/26/2004 -0700, Ray Anderson wrote:
>As Steve mentioned, the problem most likely stems from peaking in your
>supposed low pass filter network.
>The typical low pass filter that is realized with a random inductor or=20
>ferrite bead and a random capacitor (as they are usually made (not=20
>designed), isn't an impedance matched filter and exhibits peaking=20
>(typically 10 to 20 dB) somewhere near the roll-off frequency. This is
due=20
>in part to the very low impedance of the P/S driving the filter.
>
>There are several ways to fix the problem. The simplest is to put a=20
>small
>resistor in series with the inductor.
>The value needs to be small enough to not introduce excessive DC drop,
but=20
>large enough to de-Q the circuit and eliminate the objectionable
peaking.=20
>See http://si-list.org/files/tech_files/power_filt.pdf for a short=20
>document I put together a while back that describes the problem and=20
>simulation of same. For a more elegant solution, see the paper by
>Erickson ( http://ece-www.colorado.edu/~rwe/papers/APEC99.pdf ) and=20
>implement one of the filter topologies described in Figure 3 on page
2. I=20
>recommend the topology of figure 3a. which uses a shunt connected
series=20
>RC compensation network (component value calculation described in
section=20
>V.) . This circuit doesn't have the DC drop issue that the simple
series R=20
>solution has.
>
>-Ray Anderson
>
>
>
>steve weir wrote:
>
>>At 12:04 AM 8/27/2004 +0800, zhangkun 29902 wrote:
>>
>>
>>>Dear all
>>>
>>>I have a question about decoupling for PLL. In one of our PCB, there=20
>>>are
>>>three PLL. PI decoupling circuit is used. When the inductor is used,
the=20
>>>PCB does not work. When resistor of 0 ohm is used, the PCB work well.
>>>
>>
>>This is due to the inductor peaking. You can capture your clock=20
>>output
>>and put it through an FFT, and also capture the PS voltage and put it=20
>>through an FFT. The problem frequency(s) should correlate. PLLs can
be=20
>>sensitive to rather low frequency noise, some all the way down to the
KHz.
>>
>>Steve.
>>
>>
>.
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