[SI-LIST] Re: power-up sequencing
- From: steve weir <weirsp@xxxxxxxxxx>
- To: a.ingraham@xxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 17 Aug 2004 07:39:19 -0700
At 10:31 AM 8/17/2004 -0400, Andrew Ingraham wrote:
> > Generally speaking, the requirement is to keep the supplies from reversing
> > relative polarity. Reverse polarity causes bad things to happen like
> > powering through protection and parasitic diodes. If you are very unlucky
> > you will trigger a parasitic SCR and let all of the smoke out of your
> > chip.
>
>Occasionally there are chips that need it the opposite way, but I think they
>are rare. I've seen one that needed the low voltage brought up first, with
>the higher voltage not far behind it.
That's a new one on me. I have never seen that. That sounds like a logic
or PLL problem rather than substrate potential.
> > Assuming a chip has dual supply, IO and core, which one is supposed to
> > come up earlier and how much delay is expected between the two.
>
>As for delay ... I think that in general (again there may be exceptions), no
>delay is probably best. That is, the least harm would be done if all
>supplies ramp up more or less simultaneously. Holding one supply off while
>others are on, may stress the IC in a way it wasn't designed to handle.
>
> > Moreover is any glitch expected while second supply is comming up ?
>
>I think that a voltage glitch is never expected, and could be bad.
>
>A current glitch might be normal. But consult the IC manufacturer.
>
>Regards,
>Andy
>
>
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