[SI-LIST] Re: LVDS center tap capacitor termination

Shekar,

You are correct that the CM impedance is greater than 50 ohms - but not by 
much.  Is it better to have no CM termination (rho = 1), or imperfect CM 
termination (rho ~~0) for CM signals?  The single resistor provides the former, 
the split R  with cap provides the latter.

What is the CM range of your receiver?  Can it tolerate a doubling of CM noise?

Regards

Mike

shekhar sharma wrote:
> Steve,
> 
> Thanks for correction. Some mixing....
> Anyway, I think, this termination terminates the even
> mode (AC termination) upto some extent, coz the the
> resistance values are 50 ohm each with their common
> point connected to a capacitor. Diff pair with 100 ohm
> diff impedance will have common mode impedance more
> than 50 ohm.
> 
> 
>  --- steve weir <weirsp@xxxxxxxxxx> wrote: 
> 
>>You are right that it terminates both modes.  You
>>just have the modes 
>>confused.  Even is the common mode, odd is the diff.
>>mode.  The AC 
>>termination is to the even mode.
>>
>>Steve.
>>At 11:37 AM 8/30/2004 +0100, shekhar sharma wrote:
>>
>>>Two resistor with centre tap capacitor termination
>>>provides AC termination to odd-mode impedance which
>>>terminates common mode signal.
>>>May I right ???
>>>
>>>Shekh
>>>
>>>
>>> --- steve weir <weirsp@xxxxxxxxxx> wrote:
>>>
>>>>The two resistor termination is a double
>>>>single-ended termination.  The
>>>>single resistor termination presumes a virtual
>>>>ground at the center of the
>>>>resistor.
>>>>
>>>>What noise sources do you think LVDS is trying
>>
>>to
>>
>>>>reject?
>>>>What noise sources do you think LVDS can reject?
>>>>What noise sources do you think LVDS cannot
>>
>>reject?
>>
>>>>Steve.
>>>>At 03:34 PM 8/30/2004 +0530, Ummalaneni, Venu
>>
>>Babu
>>
>>>>(Venu) wrote:
>>>>
>>>>>Hi=20
>>>>>
>>>>>This query is regarding termination schemes at
>>
>>the
>>
>>>>LVDS receiver inputs.
>>>>
>>>>>Can some one explain me the difference between
>>
>>a
>>
>>>>'single resistor
>>>>
>>>>>termination' and 'the two resistors with center
>>
>>tap
>>
>>>>capacitor' ?
>>>>
>>>>>I read some where that the 'center tap
>>
>>capacitor
>>
>>>>scheme' filter's  the
>>>>
>>>>>common mode noise. My doubt is that even in
>>
>>'single
>>
>>>>resistor scheme'
>>>>
>>>>>also if we run the differential traces verly
>>>>
>>>>closely the common mode
>>>>
>>>>>noise pick-up by the two traces is equal and
>>
>>the
>>
>>>>Receiver can reject
>>>>
>>>>>this common mode part, right? So why we need to
>>
>>go
>>
>>>>for center tap
>>>>
>>>>>capacitor scheme? It unnecessarily increase the
>>>>
>>>>component count on the
>>>>
>>>>>board, right?
>>>>>
>>>>>Any inputs are appreciated.
>>>>>
>>>>>Best regards
>>>>>Venu Babu.
>>>>>
>>>>
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