Zhangkun- I think perhaps Istvan may be on to something here. Can you give us a bit more detail on your application? Three frequency of the PLL oscillator? The frequencies you are seeing the 3dB increase in 'noise' at? Have you modeled the frequency response of the power filter? Is there peaking? How much? At what frequency? The PLL power filter (ferrite bead and caps) probably has a cutoff frequency in the kHz or 10's of kHz range. It's job is to pass DC but to provide attenuation to noise above it's cutoff frequency. Assuming your PLL is running at a frequency running in the 100's of MHz then the shunt capacitors of the power filter are likely looking inductive and are not providing much bypassing of the PLL oscillator frequency. With the zero ohm resistor this mostly unattenuated VHF noise sourced by the PLL oscillator is probably being bypassed for the most part by the interplane capacitance provide by your power planes. When you put the ferrite bead or inductor in the filter circuit, the inductive reactance of the part provides a significant impedance at VHF and may be allowing you to develop a somewhat greater voltage at the PLL power pins than was observed with the zero ohm resistor. If you include the inductive parasitics of your decoupling capacitors (mounted inductance) in your simulation model of your PLL filter circuit you will find that there is considerable 'bounce-back' of attenuation at VHF frequencies (i.e., the attenuation does not continue to increase monotonically with increasing frequency). If the mounted inductance of the filter shunt elements isn't very low the bounce-back can be quite significant. The low frequency response of your filter may be pretty good, but the VHF response can be terrible if you don't pay particular attention to the design. Also, as Steve mentioned, be sure to measure this noise with a high impedance probe. Your PLL circuit probably has an impedance at the power pin of a 100 ohms or so depending on the Vdd level and the current draw. If you connect a 50 spectrum analyzer input (DC blocked) to that node you will shunt whatever noise is there through the 50 ohms and disturb the measured signal level. The high impedance probe can either be an active probe or a resistive attenuator. Be sure to use good high frequency probing technique with regard to the ground (reference) connection. -Ray Istvan NOVAK wrote: >Zhangkun, > >When you say "harmonic frequency", do you mean the >output frequency of PLL? Most of the time the output >frequency is much higher than the PLL's filter bandwidth, >which is usually in the hundreds of kHz. PLLs tend to >be sensitive to noise on their analog supply pin at or >below the filter bandwidth. Have you also compared the >noise below 1MHz? > >Regards, >Istvan > > > . ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu