Posts for si-list, 07-2004

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» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: si-list Digest V4 #302 -
» [SI-LIST] Re: about XAUI error -
» [SI-LIST] Andreas Graevinghoff/DE/ETAS is out of office. -
» [SI-LIST] about XAUI error -
» [SI-LIST] Announcement: Mayo EM Solver Software Available -
» [SI-LIST] Fwd: Re: Re: Drivers on a 50Ohm line -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] DesignCon 2005 call for papers -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] Re: DDR DRAM -
» [SI-LIST] DDR DRAM -
» [SI-LIST] Subject: SI Simulation of GHz signals_28Jul04 -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] Re: resitor packs vs networks in DDR design -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] resitor packs vs networks in DDR design -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: si-list: clifford@blackhole.net post needs approval -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] Re: Drivers on a 50Ohm line -
» [SI-LIST] Drivers on a 50Ohm line -
» [SI-LIST] Re: DDR Eye diagrams -
» [SI-LIST] Re: AW: DDR Eye diagrams -
» [SI-LIST] AW: AW: DDR Eye diagrams -
» [SI-LIST] Re: AW: DDR Eye diagrams -
» [SI-LIST] Re: AW: DDR Eye diagrams -
» [SI-LIST] AW: DDR Eye diagrams -
» [SI-LIST] Re: DDR Eye diagrams -
» [SI-LIST] DDR Eye diagrams -
» [SI-LIST] Re: Oscilloscope probe modeling -
» [SI-LIST] SDRAM output impedance -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: [Bulk] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: series resistor on SSTL-2 -
» [SI-LIST] Oscilloscope probe modeling -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: DRAM Address lines : Daisy Chain or "T"? -
» [SI-LIST] DRAM Address lines : Daisy Chain or "T"? -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: series resistor on SSTL-2 -
» [SI-LIST] Manipulation of ICM and/or ICEM model in EDA tool -
» [SI-LIST] Re: Hspice with IBIS model containing driver schedule -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SPICE for LINUX -
» [SI-LIST] Re: SPICE for LINUX -
» [SI-LIST] Re: Sr. Signal Integrity Engineer opportunity -
» [SI-LIST] series resistor on SSTL-2 -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] Sr. Signal Integrity Engineer opportunity -
» [SI-LIST] Re: SI Simulation of GHz signals -
» [SI-LIST] SI Simulation of GHz signals -
» [SI-LIST] Smart Voltage Regulator for PCI Card -
» [SI-LIST] Re: skin effect -
» [SI-LIST] Re: skin effect -
» [SI-LIST] Re: skin effect -
» [SI-LIST] Re: SPICE for LINUX -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: skin effect -
» [SI-LIST] Re: skin effect -
» [SI-LIST] -
» [SI-LIST] Re: skin effect -
» [SI-LIST] skin effect -
» [SI-LIST] Re: xtk application crashes -
» [SI-LIST] Re: SPICE for LINUX -
» [SI-LIST] SPICE for LINUX -
» [SI-LIST] SPICE for LINUX -
» [SI-LIST] Re: xtk application crashes -
» [SI-LIST] xtk application crashes -
» [SI-LIST] Hi,all. How can we do if DDRI and DDR2 are laid in the same trace? How to deal with the termination? thanks! -
» [SI-LIST] Re: EMI simulation tools -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] LVTTL to HSTL -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] ECL model -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to interpret Jitter Specification -
» [SI-LIST] How to interpret Jitter Specification -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] Re: Dear, can anybody tell me what's the max overshoot and min undershoot value of PCI? thank you! -
» [SI-LIST] Re: The precision of Ansoft Maxwell 2D -
» [SI-LIST] The precision of Ansoft Maxwell 2D -
» [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] Re: question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] question regarding Ansoft Maxwell 2D repetitive simulations -
» [SI-LIST] Re: Low noise electronics and Xilinx high-speed links -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Low noise electronics and Xilinx high-speed links -
» [SI-LIST] Low noise electronics and Xilinx high-speed links -
» [SI-LIST] the relation between speed grade and rising time of altera fpga devices -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: SSTL Standard -
» [SI-LIST] Re: PCI -
» [SI-LIST] LVTTL to CML -
» [SI-LIST] SSTL Standard -
» [SI-LIST] PCI -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] (no subject) -
» [SI-LIST] 回信： How to measure voltage drop on plane -
» [SI-LIST] IBIS Open_source and ECL models -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: TDR on Package only -
» [SI-LIST] TDR on Package only -
» [SI-LIST] Re: How to measure voltage drop on plane -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] How to measure voltage drop on plane -
» [SI-LIST] Re: Return path -
» [SI-LIST] AW: Return path -
» [SI-LIST] Re: Return path -
» [SI-LIST] Re: Return path -
» [SI-LIST] Return path -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: Digest Number 1151 -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: PCB rework speciality houses -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: guard traces (huge) -
» [SI-LIST] Re: What is ASTAP? -
» [SI-LIST] What is ASTAP? -
» [SI-LIST] guard traces (huge) -
» [SI-LIST] Re: primary question about spread spectrum clock -
» [SI-LIST] Re: primary question about spread spectrum clock -
» [SI-LIST] primary question about spread spectrum clock -
» [SI-LIST] Dear, can anybody tell me what's the max overshoot and min undershoot value of PCI? thank you! -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Ground bounce -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Hi,dear all:What's the function of damping resistor between MCH and DIMM slot? Only reduce current? -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: Via Impedance! -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: Hspice with IBIS model containing driver schedule -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] R: Hspice with IBIS model containing driver schedule -
» [SI-LIST] Re: Hspice with IBIS model containing driver schedule -
» [SI-LIST] Hspice with IBIS model containing driver schedule -
» [SI-LIST] 回信： Ground bounce -
» [SI-LIST] Re: Ground bounce -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] Ground bounce -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: IBIS file data -
» [SI-LIST] Re: Via Impedance! -
» [SI-LIST] IBIS file data -
» [SI-LIST] Re: Via modeling & de-embedding -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] The function of damping resistor between MCH and DIMM slot -
» [SI-LIST] Can SSTL float? -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] R: Re: Via Impedance! -
» [SI-LIST] Re: Heatsink acting as EMI shield. -
» [SI-LIST] Heatsink acting as EMI shield. -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: diffusion capacitance measurement -
» [SI-LIST] Re: diffusion capacitance measurement -
» [SI-LIST] Re: diffusion capacitance measurement -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: diffusion capacitance measurement -
» [SI-LIST] Re: HSPICE question -
» [SI-LIST] Re: HSPICE question -
» [SI-LIST] Re: Allegro -
» [SI-LIST] HSPICE question -
» [SI-LIST] Re: PCB rework speciality houses -
» [SI-LIST] FW: Allegro -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: Allegro -
» [SI-LIST] Re: PCB rework speciality houses -
» [SI-LIST] Re: Via Impedance! -
» [SI-LIST] Re: New 2004 textbook out on high-speed design and signal integrity -
» [SI-LIST] Re: New 2004 textbook out on high-speed design and signal integrity -
» [SI-LIST] Re: Allegro -
» [SI-LIST] New 2004 textbook out on high-speed design and signal integrity -
» [SI-LIST] Allegro -
» [SI-LIST] diffusion capacitance measurement -
» [SI-LIST] Via Impedance! -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: why the step should be 0.05ns? -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: A question in 2D Extractor & HFSS -
» [SI-LIST] Re: Automotive ECU EMI problems -
» [SI-LIST] Automotive ECU EMI problems -
» [SI-LIST] A question in 2D Extractor & HFSS -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] R: IBIS models for Pb-free (lead-free) BGA package -
» [SI-LIST] Re: High Speed Termination -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: The future of si-list -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: DDR point to point termination -
» [SI-LIST] Re: The future of si-list -
» [SI-LIST] DDR point to point termination -
» [SI-LIST] Re: why the step should be 0.05ns? -
» [SI-LIST] Naveen Reddy -
» [SI-LIST] why the step should be 0.05ns? -
» [SI-LIST] noise measurement literature -
» [SI-LIST] Re: Vector Fitting Matlab Code Request -
» [SI-LIST] IBIS models for Pb-free (lead-free) BGA package -
» [SI-LIST] Vector Fitting Matlab Code Request -
» [SI-LIST] PCB rework speciality houses -
» [SI-LIST] Re: High Speed Termination -
» [SI-LIST] High Speed Termination -
» [SI-LIST] Re: balun theory -
» [SI-LIST] Just Testing -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: add new power island in a 8 layer stack -
» [SI-LIST] many irregular Tr-Line and smash GND Plane -
» [SI-LIST] The future of si-list -
» [SI-LIST] RMCEMC June presentation download available -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: balun theory -
» [SI-LIST] Re: a problem in simulate crystal oscillator -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: balun theory -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: add new power island in a 8 layer stack -
» [SI-LIST] Re: add new power island in a 8 layer stack -
» [SI-LIST] Re: balun theory -
» [SI-LIST] Re: balun theory -
» [SI-LIST] balun theory -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] add new power island in a 8 layer stack -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: a problem in simulate crystal oscillator -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] a problem in simulate crystal oscillator -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Loading IBIS in Signoise! -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Loading IBIS in Signoise! -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Is Impedance Enough for Describing the PDS? -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: Differential pair via modeling -
» [SI-LIST] Re: spliting lvds clk -
» [SI-LIST] spliting lvds clk -
» [SI-LIST] Re: six layer, eight layer, other -
» [SI-LIST] Course on Signal Integrity at San Jose State University -
» [SI-LIST] Re: Differential pair via modeling -
» [SI-LIST] Re: Differential pair via modeling -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: Need to buy standards book or manual -
» [SI-LIST] Re: six layer, eight layer, other -
» [SI-LIST] six layer, eight layer, other -
» [SI-LIST] Re: Ansoft's SI-wave? -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: Need to buy standards book or manual -
» [SI-LIST] Re: High Speed PCB design standards -
» [SI-LIST] Re: Need to buy standards book or manual -
» [SI-LIST] Need to buy standards book or manual -
» [SI-LIST] High Speed PCB design standards -
» [SI-LIST] Field coupling from an impulse event -
» [SI-LIST] Ansoft's SI-wave? -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: si-list Digest V4 #261 -
» [SI-LIST] Re: si-list Digest V4 #261 -