Posts for si-list, 06-2008

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  1. » [SI-LIST] PCB Parasitics, sunil bharadwaz
  2. » [SI-LIST] S-par to Spice, Saoer Sinaga
  3. » [SI-LIST] Re: S-par to Spice, Antonio Ciccomancini Scogna
  4. » [SI-LIST] Re: loop antenna (mis)behavior, Richard Jungert
  5. » [SI-LIST] Agenda, IBIS Summit Meeting, June10th - DAC2008 (UPDATED), Syed Huq (shuq)
  6. » [SI-LIST] Agenda, IBIS Summit Meeting, June 10th during DAC2008, Mirmak, Michael
  7. » [SI-LIST] Buried capacitance layer; ? Area to use? Use with discrete caps?, tom_cip_11551
  8. » [SI-LIST] ethernet, joseph saddlers
  9. » [SI-LIST] Minimize SSN and Jitter with Advanced Transceiver Technology, Salman Jiva
  10. » [SI-LIST] SPICE netlist to Verilog Gate level, James Church
  11. » [SI-LIST] Contract job in Fremont, CA, Kevin Pierpoint
  12. » [SI-LIST] Shielded loop parasitic coupling, Douglas Smith
  13. » [SI-LIST] [Fwd: Shielded loop parasitic coupling] the missing link, Douglas Smith
  14. » [SI-LIST] How to calculate/obtain footprint ind/cap characteristic for 402, 603, etc?, tom_cip_11551
  15. » [SI-LIST] Stressed-eye tests, Radhakrishnan, Nitin (S&T-Student)
  16. » [SI-LIST] June Issue of XrossTalk Magazine Available, Timothy Coyle
  17. » [SI-LIST] SI tool upgrade, Ke
  18. » [SI-LIST] About power ripple test, Han Li
  19. » [SI-LIST] transister width Optimization, navaram kumar
  20. » [SI-LIST] Re: transister width Optimization, olaney
  21. » [SI-LIST] cascading s-parameter blocks, Michael Rose
  22. » [SI-LIST] Ethernet Related, Anand Srinivasan
  23. » [SI-LIST] How to calculated the resonance frequency of transformer., Lijun
  24. » [SI-LIST] Adding cyrstal oscillator to PCB, Christopher.Jakubiec
  25. » [SI-LIST] Packaging Design Engineer Opening at Altera Corporation, Geping Liu
  26. » [SI-LIST] EPEP 2008 Call For Papers, Paul D. Franzon
  27. » [SI-LIST] senior EMC engineer positions at Huawei (China or Dallas), Geping Liu
  28. » [SI-LIST] New SI-Insights #3 posted on beTheSignal.com, Eric Bogatin
  29. » [SI-LIST] How to do crystal simulation, 靖 李
  30. » [SI-LIST] Trasformer IBIS Model, Umamaheswar U-TLS,Chennai
  31. » [SI-LIST] Re: How to do crystal simulation, 靖 李
  32. » [SI-LIST] Re: How to use s-parameter generated from specctra-quest in, Dmitriev-Zdorov, Vladimir
  33. » [SI-LIST] CAREER OPPORTUNITY : Signal Integrity Engineer (Hardware Engineer), Mahalakshmi Srinivasan -X (mahasrin - Ma Foi at Cisco)
  34. » [SI-LIST] SPICE to IBIS, Mohamad Haghtalab
  35. » (no subject), Ambr Amit
  36. » [SI-LIST] Re: Power/ground BGA assignment in package, Ambr Amit
  37. » [SI-LIST] Signal Integrity Engineer, bruce harvie
  38. » [SI-LIST] Re: Number of layers, Dan Bostan
  39. » [SI-LIST] cPCI backplane signal traces - characteristic impedance, Sexton, Brian M. \(US SSA\)
  40. » [SI-LIST] Lab Tech/Manager Position - Andover MA, Haller, Robert
  41. » [SI-LIST] Re: Lab Tech/Manager Position - Andover MA, olaney
  42. » [SI-LIST] CAREER OPPORTUNITY : Signal Integrity Engineer (Hardware Engineer) - Bangalore, Mahalakshmi Srinivasan -X (mahasrin - Ma Foi at Cisco)
  43. » [SI-LIST] anybody can help to recommend good ESD document or book?Thanks!, yinhongcheng
  44. » [SI-LIST] IBIS Fast-Strong/Typ/Slow-Weak Corners, M. Haaeri
  45. » [SI-LIST] Re: anybody can help to recommend good ESD document or book?Thanks!, yinhongcheng
  46. » [SI-LIST] CST Application Engineer Opening, Ray Anderson
  47. » [SI-LIST] near field, Mohamad Haghtalab
  48. » [SI-LIST] Does anyone use "buried capacitance" layers?, tom_cip_11551
  49. » [SI-LIST] IBIS Summit presentations now on-line!, Mirmak, Michael
  50. » [SI-LIST] Re: Does anyone use "buried capacitance" layers?, istvan.novak
  51. » [SI-LIST] DDR3 SI and Timing analysis, Cristian Filip
  52. » [SI-LIST] conductor losses, Saoer Sinaga
  53. » [SI-LIST] max transient current in target impedance calculation, Wu, Jing
  54. » [SI-LIST] Fw: SI engineer job opportunities at Hisilicon (huawei) in Shanghai or Shenzheng, China, yinhongcheng
  55. » [SI-LIST] SIGNAL INTEGRITY ENGINEER \x96 Juniper Networks ? Sunnyvale, CA, admin
  56. » [SI-LIST] Signal Integrity Engineer - Juniper Networks - Sunnyvale, CA, Ralph Kettler