[SI-LIST] transister width Optimization
- From: "navaram kumar" <knavaram@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 10 Jun 2008 19:46:20 +0530
Hi all,
I am Cadence ADE for transister Width Optimization. In that it is giving
different result depending on the intial values and the Variable range. My
Doubt is how to give good intial values that will lead optimum width.
I am flip flop design, I have to compare the two designs, and tell which
one is better. In the papers all Optimized their designs for Min Power Delay
Product an compared. I have to do the same but I am facing problem.
Could any body suggest any book or any paper.
Thanks Regards
K.Navaram Kumar
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