[SI-LIST] Re: transister width Optimization
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 10 Jun 2008 10:42:11 -0700
Navaram-
I think you missed the point of the question (how does this relate to
signal integrity?). si-list is a signal integrity forum where the aim is
to have the technical discussions at least tangentially related to SI.
It sound like your inquiry would more appropriately posed to an IC
design forum.
-Ray
(si-list admin)
(ray.anderson@xxxxxxxxxx)
> =
> It is not related to signal integrity ( up my knowledge). if we are
> designin
> any digital circuit we wiil design for some target delay. This delay
can
> be
> achived different combinations transister width which will have power.
we
> have to design design which will consume less power . Like this for
> different delays we have to mesure power. For some delay Product of
POWER
> AND DELAY will be the minmum this is call min POWER DELAY PRODUCT . I
am
> traying to do this
> On 10/06/2008, navaram kumar <knavaram@xxxxxxxxx> wrote:
> >
> > Hi all,
> >
> > I am Cadence ADE for transister Width Optimization. In that it is
giving
> > different result depending on the intial values and the Variable
range.
> My
> > Doubt is how to give good intial values that will lead optimum
width.
> > I am flip flop design, I have to compare the two designs, and tell
> which
> > one is better. In the papers all Optimized their designs for Min
Power
> Delay
> > Product an compared. I have to do the same but I am facing
problem.
> > Could any body suggest any book or any paper.
> > Thanks Regards
> > K.Navaram Kumar
> >
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