(no subject)

Hi,

    I'm working on a 6-layer flipchip package design with following stackup:





VSS


signal


VDD


VSS


VDD


Balls





    This package gets used on a 4-layer board with stackup of





signal


VSS


VDD


signal





    The design supports high speed interfaces like
DDR3-1600 & multiple Serdes (upto 5Gbps). While doing ball
assignment I'm proposing to place power/ground (VDD/VSS) balls in the
perimeter of package (to get better return paths for high speed
signals). But based on the board routing this is turning out to be bad
idea because it blocks lot of signal routes and proposal is to move all
the power/ground (VDD/VSS) inside towards the centre of the package.
I'm not comfortable with this because 





- this will affect the return path 


- it results in current crowding in the central area where lot of VDD/VSS balls 
are places


- and ineffective use of package internal planes





     This can result in SI issues. But sadly I do
not have any data which can support that moving all the VDD/VSS towards
centre will result in SI issues. One part is doing simulation to see
the impact of bad return path, which I'm working on. But if someone in
SI-list has already done study on this scenario, I would appreciate
their opinions and data on this subject.





Thanks and regards


Amit





      
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