Posts for si-list, 07-2008

Browse: Last Month: 06-2008 Main Archive Page Next Month: 08-2008

» [SI-LIST] Jingling change, ESD, and scope probes video -
» [SI-LIST] Re: Number of Power Planes in a Stack up -
» [SI-LIST] Re: signal quality on unbuffered DIMM -
» [SI-LIST] Re: the effect of box on EMI -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: signal quality on unbuffered DIMM -
» [SI-LIST] 回复:RE: the effect of box on EMI -
» [SI-LIST] Re: R: Re: Ansoft License issue -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Number of Power Planes in a Stack up -
» [SI-LIST] Re: IBIS Ver 4.2&5 -
» [SI-LIST] Great Blog Colin! -
» [SI-LIST] Re: the effect of box on EMI -
» [SI-LIST] Re: Indcutance role in EMI -
» [SI-LIST] Re: Indcutance role in EMI -
» [SI-LIST] Indcutance role in EMI -
» [SI-LIST] 答复: the effect of box on EMI -
» [SI-LIST] Re: the effect of box on EMI -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: the effect of box on EMI -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: the effect of box on EMI -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] Re: How to short two nodes in SPICE -
» [SI-LIST] the effect of box on EMI -
» [SI-LIST] How to short two nodes in SPICE -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] R: Re: Ansoft License issue -
» [SI-LIST] DDR2 Setup/Hold Derating -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Enterprise Network Switching DDR & SerDes Interface Design Manager -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] Re: 12 Layer stack -
» [SI-LIST] 12 Layer stack -
» [SI-LIST] Re: Ansoft License issue -
» [SI-LIST] Re: My new SI blog -
» [SI-LIST] Re: current distribution -
» [SI-LIST] Re: current distribution -
» [SI-LIST] Email test <D, please ignore. -
» [SI-LIST] mail test, please ignore. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: current distribution -
» [SI-LIST] current distribution -
» [SI-LIST] Re: Would you follow the overshoot specs of the datasheet? -
» [SI-LIST] Re: Would you follow the overshoot specs of the datasheet? -
» [SI-LIST] Re: IBIS Ver 4.2&5 -
» [SI-LIST] IBIS Ver 4.2&5 -
» [SI-LIST] 回复:Re: Would you follow the overshoot specs of the datasheet? -
» [SI-LIST] Re: Would you follow the overshoot specs of the datasheet? -
» [SI-LIST] Would you follow the overshoot specs of the datasheet? -
» [SI-LIST] Re: power consuming of IC in different temperature -
» [SI-LIST] Signal Integrity Position in DuPont, Washington -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: power consuming of IC in different temperature -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] 回复:dendrites / edge relief -
» [SI-LIST] Re: power consuming of IC in different temperature -
» [SI-LIST] Re: power consuming of IC in different temperature -
» [SI-LIST] power consuming of IC in different temperature -
» [SI-LIST] Re: new video podcast "A Scope Probe can Fool You" -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] dendrites / edge relief -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification [test, ignore] -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Free, hands-on PCIe Workshop: Signal Integrity Design, Analysis, and Verification -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: Multiple series caps in signal lines -
» [SI-LIST] Re: Multiple series caps in signal lines -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] new video podcast "A Scope Probe can Fool You" -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: My new SI blog -
» [SI-LIST] My new SI blog -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: Multiple series caps in signal lines -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Re: Hspice Simulation problem! -
» [SI-LIST] Hspice Simulation problem! -
» [SI-LIST] Senior Applications Engineer - Inphi Corporation - Sunnyvale, CA or Westlake Village, CA -
» [SI-LIST] Re: Multiple series caps in signal lines -
» [SI-LIST] Multiple series caps in signal lines -
» [SI-LIST] Re: SATA Receive signal criteria -
» [SI-LIST] A warning in ADS simulation -
» [SI-LIST] Re: SATA Receive signal criteria -
» [SI-LIST] Signal Integrity Engineer - NetLogic Microsystems - Mountain View, CA -
» [SI-LIST] video on PCB troubleshooting -
» [SI-LIST] Re: An S-Parameter matrix to look differential mode crosstalk? -
» [SI-LIST] An S-Parameter matrix to look differential mode crosstalk? -
» [SI-LIST] DDR2 Trace Length Margin -
» [SI-LIST] Re: DDR2 Trace Length Margin -
» [SI-LIST] Draft IBIS 5.0 specification now available for review -
» [SI-LIST] SATA Receive signal criteria -
» [SI-LIST] I am looking for a "good" macromodel dml for MGH simulation -
» [SI-LIST] DDR2 Trace Length Margin -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: ESS TC failure @ - 20C or -40C -
» [SI-LIST] ESS TC failure @ - 20C or -40C -
» [SI-LIST] 10 Layer stack up -
» [SI-LIST] EPEP 2008 Call For Papers -
» [SI-LIST] Eric Bogatin's new SI blog -
» [SI-LIST] LVCMOS to HSTL -
» [SI-LIST] SI books & software for sale -
» [SI-LIST] Re: trivial newbie question -
» [SI-LIST] Re: trivial newbie question -
» [SI-LIST] Re: trivial newbie question -
» [SI-LIST] Re: trivial newbie question -
» [SI-LIST] Re: trivial newbie question -
» [SI-LIST] A powerful troubleshooting technique -
» [SI-LIST] trivial newbie question -
» [SI-LIST] R: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Job Opening, Altera High-Speed Characterization -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Need help -
» [SI-LIST] Re: Need help -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Need help -
» [SI-LIST] Need help -
» [SI-LIST] Re: Signal integrity -
» [SI-LIST] Re: Signal intergrity -
» [SI-LIST] Fwd: [Help] How to implement filter function in Ansoft Nexxim -
» [SI-LIST] Re: Signal intergrity -
» [SI-LIST] Re: How to decide the cut off frequency in SIwave -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Recruitment -
» [SI-LIST] weekly video podcasts -
» [SI-LIST] Re: Signal integrity -
» [SI-LIST] Re: DDR2 Simulation -
» [SI-LIST] DDR2 Simulation -
» [SI-LIST] Fw: Re: MD-Spice -
» [SI-LIST] Re: MD-Spice -
» [SI-LIST] MD-Spice -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: Signal intergrity -
» [SI-LIST] short video on building a square magentic loop -
» [SI-LIST] Signal intergrity -
» [SI-LIST] Re: What will happen when short the SERDES IO to GND? -
» [SI-LIST] Re: Information regarding Stackup Design. -
» [SI-LIST] Re: What will happen when short the SERDES IO to GND? -
» [SI-LIST] Re: DDR2 VTT terminations -
» [SI-LIST] Re: 8 layer PCB stackups and microvias -
» [SI-LIST] Re: How to decide the cut off frequency in SIwave -
» [SI-LIST] Re: 8 layer PCB stackups and microvias -
» [SI-LIST] Re: DDR2/DDR3 -
» [SI-LIST] Information regarding Stackup Design. -
» [SI-LIST] Re: DDR2/DDR3 -
» [SI-LIST] Re: 8 layer PCB stackups and microvias -
» [SI-LIST] Re: PCB Laminate - Nelco & S1000-2 -
» [SI-LIST] Re: PCB Laminate - Nelco & S1000-2 -
» [SI-LIST] Re: DDR2 VTT terminations -
» [SI-LIST] Re: DDR2/DDR3 -
» [SI-LIST] 8 layer PCB stackups and microvias -
» [SI-LIST] Re: PCB Laminate - Nelco & S1000-2 -
» [SI-LIST] Re: DDR2 VTT terminations -
» [SI-LIST] DDR2 VTT terminations -
» [SI-LIST] Re: DDR2/DDR3 -
» [SI-LIST] PCB Laminate - Nelco & S1000-2 -
» [SI-LIST] DDR2/DDR3 -
» [SI-LIST] Re: What will happen when short the SERDES IO to GND? -
» [SI-LIST] Re: What will happen when short the SERDES IO to GND? -
» [SI-LIST] What will happen when short the SERDES IO to GND? -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Has the performance of the PDN in the receiver little effect on the SSN? -
» [SI-LIST] Re: Has the performance of the PDN in the receiver little effect on the SSN? -
» [SI-LIST] Re: Has the performance of the PDN in the receiver little effect on the SSN? -
» [SI-LIST] Has the performance of the PDN in the receiver little effect on the SSN? -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Signal Integrity programs at upcoming IEEE International Symposium on EMC (August 18 - 22, Detroit, USA) -
» [SI-LIST] How to decide the cut off frequency in SIwave -
» [SI-LIST] Virtex -5 PCI ibis file and simulation -
» [SI-LIST] Re: Termination method for Bi-Directional data Bus connecting a number of devices. -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Termination method for Bi-Directional data Bus connecting a number of devices. -
» [SI-LIST] Re: Termination method for Bi-Directional data Bus connecting a number of devices. -
» [SI-LIST] Termination method for Bi-Directional data Bus connecting a number of devices. -
» [SI-LIST] Parasitic Coupling Between Unshielded Wire Loops -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: RF switch information -
» [SI-LIST] Re: RF switch information -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: RF switch information -
» [SI-LIST] RF switch information -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Reg reference plane :speed2000 -
» [SI-LIST] Reg reference plane :speed2000 -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: [!! SPAM] Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: Looking for good source of information regarding Via tuning -
» [SI-LIST] Looking for good source of information regarding Via tuning -
» [SI-LIST] Re: power integrity test plan -
» [SI-LIST] Re: power integrity test plan -
» [SI-LIST] Re: Power/ground BGA assignment in package -
» [SI-LIST] power integrity test plan -
» [SI-LIST] Re: max transient current in target impedance calculation -
» [SI-LIST] Re: max transient current in target impedance calculation -
» [SI-LIST] Re: max transient current in target impedance calculation -