[SI-LIST] Re: Number of layers
- From: Dan Bostan <dbostan@xxxxxxxxx>
- To: Ambr Amit <ambr_amit@xxxxxxxxx>
- Date: Mon, 23 Jun 2008 10:47:30 -0700 (PDT)
Why use only four layers for the board?
In order to break the signals properly under the chip you (probably) need six
layers for the board.
Going that way you would improve the SI.
/dan
----- Original Message ----
From: Ambr Amit <ambr_amit@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Monday, June 23, 2008 7:01:10 AM
Subject: (no subject)
Hi,
I'm working on a 6-layer flipchip package design with following stackup:
VSS
signal
VDD
VSS
VDD
Balls
This package gets used on a 4-layer board with stackup of
signal
VSS
VDD
signal
The design supports high speed interfaces like
DDR3-1600 & multiple Serdes (upto 5Gbps). While doing ball
assignment I'm proposing to place power/ground (VDD/VSS) balls in the
perimeter of package (to get better return paths for high speed
signals). But based on the board routing this is turning out to be bad
idea because it blocks lot of signal routes and proposal is to move all
the power/ground (VDD/VSS) inside towards the centre of the package.
I'm not comfortable with this because
- this will affect the return path
- it results in current crowding in the central area where lot of VDD/VSS balls
are places
- and ineffective use of package internal planes
This can result in SI issues. But sadly I do
not have any data which can support that moving all the VDD/VSS towards
centre will result in SI issues. One part is doing simulation to see
the impact of bad return path, which I'm working on. But if someone in
SI-list has already done study on this scenario, I would appreciate
their opinions and data on this subject.
Thanks and regards
Amit
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