[SI-LIST] Re: Number of layers
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Salkow, Steven" <steven.salkow@xxxxxxxx>
- Date: Mon, 23 Jun 2008 12:36:51 -0700
Steven one nit. What bypass caps in the package do primarily is support
the Vcc rail, which is a very good thing. Bypass caps in the package
are very limited in what they can do vis-a-vis ground bounce.
With sufficient coupling through bypass caps/power cavities/die
capacitance, return currents can be balanced between Vcc and Vss and the
PCB PROVIDED that the PCB also has to have tight coupling between Vcc
and Vss. This doesn't happen in cheapy four layer boards, so what Intel
intelligently does is follow one of Chris Cheng's mantras and insure
that the signals route through the PCB referencing the same power rail
that they reference in the package. In this way, it is not necessary to
ballast big, fast parallel busses through the PDN. DDR references DQ
and DQS to Vss and address and control to Vdd end to end for this reason.
Minimizing bounce is a matter of providing sufficiently low return path
impedance, which is primarily a matter of the interconnect design. In
Xilinx' case, they address this through much improved distribution of
Vss balls through the I/O pin field in V4 and V5 than earlier designs.
Best Regards,
Steve.
Salkow, Steven wrote:
> Picture is worth a 1000 words. (See my website:
> http://www.bychoice.com/XC2VP70_6FF1704C.jpg
>
> This is a Xilinx part from one of our designs with the GND pins
> highlighted. You can see what they have done. The layout of an IC and
> the ability to PIN it out is always a compromise. Xilinx, however, has
> done something rather smart as far as decoupling the IC has they have
> included capacitance in their packaging that minimizes the effect of
> ground bounce. The complex nature of electronic packaging has kept many
> fine electronic engineers employed for life and that cannot be conveyed
> in an email. Many designs, like PC are executed in 4 layers as it's real
> cheap. To make that even practical, SI engineers at Intel and other
> companies often iteratively redesign the board chip sets and even the
> processor until they have something that works. Are these OPTIMUM
> solutions as far as signal integrity? -- Absolutely not.
>
> The number of pins, the amount of signals switching at the same time,
> the pin inductance, differential coupling, amount of power needed, etc.
> . .
>
> This app note from Xilinx may help a lot:
> http://china.xilinx.com/support/documentation/application_notes/xapp623.
> pdf
>
> Good Luck
> Steve Salkow
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Dan Bostan
> Sent: Monday, June 23, 2008 10:48 AM
> To: Ambr Amit
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Number of layers
>
> Why use only four layers for the board?
> In order to break the signals properly under the chip you (probably)
> need six layers for the board.
> Going that way you would improve the SI.
> /dan
>
> ----- Original Message ----
> From: Ambr Amit <ambr_amit@xxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Monday, June 23, 2008 7:01:10 AM
> Subject: (no subject)
>
> Hi,
>
> I'm working on a 6-layer flipchip package design with following
> stackup:
>
>
>
>
>
> VSS
>
>
> signal
>
>
> VDD
>
>
> VSS
>
>
> VDD
>
>
> Balls
>
>
>
>
>
> This package gets used on a 4-layer board with stackup of
>
>
>
>
>
> signal
>
>
> VSS
>
>
> VDD
>
>
> signal
>
>
>
>
>
> The design supports high speed interfaces like
> DDR3-1600 & multiple Serdes (upto 5Gbps). While doing ball
> assignment I'm proposing to place power/ground (VDD/VSS) balls in the
> perimeter of package (to get better return paths for high speed
> signals). But based on the board routing this is turning out to be bad
> idea because it blocks lot of signal routes and proposal is to move all
> the power/ground (VDD/VSS) inside towards the centre of the package.
> I'm not comfortable with this because
>
>
>
>
>
> - this will affect the return path
>
>
> - it results in current crowding in the central area where lot of
> VDD/VSS balls are places
>
>
> - and ineffective use of package internal planes
>
>
>
>
>
> This can result in SI issues. But sadly I do
> not have any data which can support that moving all the VDD/VSS towards
> centre will result in SI issues. One part is doing simulation to see
> the impact of bad return path, which I'm working on. But if someone in
> SI-list has already done study on this scenario, I would appreciate
> their opinions and data on this subject.
>
>
>
>
>
> Thanks and regards
>
>
> Amit
>
>
>
>
>
>
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--
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