[SI-LIST] Re: DDR3 SI and Timing analysis
- From: "Kaufer, Steve" <steve_kaufer@xxxxxxxxxx>
- To: "Cristian Filip" <cris_filip2002@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 25 Jun 2008 22:06:09 -0700
Hi Christian,
You're on the right track using HyperLynx for this simulation, because
the next version (just about to go into beta testing) has complete
support for DDR2 and 3 batch-mode SI simulation and timing analysis. If
you contact me off-line, I can arrange to get you into the beta program.
I can also find someone to help you with your other detailed questions.
Regards,
Steve Kaufer,
Engineering Director,
Mentor Graphics
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Cristian Filip
Sent: Wednesday, June 25, 2008 7:51 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR3 SI and Timing analysis
DDR3 SI and Timing analysis
Hello,
I am working on a DDR3 interface and the final outcome should be the
comple=3D te SI and Timing analysis. We are using Mentor tools =
(HyperLynx,
ICX Pro & =3D
ICX) and I am just at the beginning of this process. I am sure that
until t=3D he end I will have more questions on this topic and this is =
why
I preferred=3D to give the actual title to this message and not a more
specific one. I am=3D sure also that other people on this group are
facing similar situations, s=3D o we might exchange some of our
experiences.
The supplier of the Memory Controller has provided the IBIS model of the
di=3D e and four Package Electrical models in HSPICE format extracted
using Ansof=3D t Q3D Extractor. We got also a schematic diagram which
specifies the order =3D
(serial) we have to follow to connect those models.=3D20
On the memory side we are going to use SODIMM=3DE2=3D80=3D99s and we got =
the
EBD =3D and IBIS models for those DIMM=3DE2=3D80=3D99s from our =
supplier.=3D20
I have tried to do some pre-layout simulations in LineSim using the
models =3D provided and on a very simple point to point DQ topology I =
got
a very ugly =3D signal at the DIMMs, which seem to be determined by a =
huge
attenuation intr=3D oduced by the package parasitic, so I decided to
validate my model before t=3D o investigate the spice models.=3D20
From the IBIS model I determined that Vref =3D3D1.5V, Rref =3D3D50Ohms =
and
Cref=3D =3D3D0. Many documents I have read are suggesting that the test =
load
would be=3D in this case a simple pull-up resistor connected to a 1.5V
power rail. I d=3D id try and the results of simulation are showing a DC
offset, so the Vol DC=3D =3D3D600mV > Vil DC=3D3D595Mv, which tells me =
that
the test circuit isn=3DE2=3D80=3D =3D99t the right one. If I replace the =
Vref
with 0.75V the output signal make=3D s sense.=3D20
The questions that arise are:=3D20
=3DE2=3D80=3DA2Are the Vref, Rref and Cref the parameters describing the =
test
loa=3D d?
=3DE2=3D80=3DA2If yes, this holds true even if the IBIS model is =
actually the
mod=3D el of the die?
=3DE2=3D80=3DA2If we add to the IBIS models the series Spice parasitic =
models
the=3D test load will still be described by those parameters?
=3DE2=3D80=3DA2What would be the best way of using this combination of
IBIS-HSPIC=3D E models in LineSim and BoardSim?
=3DE2=3D80=3DA2It is possible to run batch mode simulation in BoardSim =
using
this=3D combination of models?
=3DE2=3D80=3DA2If in top of those we add some timing models what would =
be the
com=3D bined solution to do SI and timing analysis?
=3DE2=3D80=3DA2It is ICX or ICX Pro (Explorer and Verify) more suitable =
for
this =3D kind of situation?
Thank you in advance,
Cristian Filip
=3D0A=3D0A=3D0A
____________________________________________________________=3D
______=3D0AYahoo! Canada Toolbar: Search from anywhere on the web, and
bookma=3D rk your favourite sites. Download it now
at=3D0Ahttp://ca.toolbar.yahoo.com.
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