DDR3 SI and Timing analysis Hello, I am working on a DDR3 interface and the final outcome should be the comple= te SI and Timing analysis. We are using Mentor tools (HyperLynx, ICX Pro & = ICX) and I am just at the beginning of this process. I am sure that until t= he end I will have more questions on this topic and this is why I preferred= to give the actual title to this message and not a more specific one. I am= sure also that other people on this group are facing similar situations, s= o we might exchange some of our experiences. The supplier of the Memory Controller has provided the IBIS model of the di= e and four Package Electrical models in HSPICE format extracted using Ansof= t Q3D Extractor. We got also a schematic diagram which specifies the order = (serial) we have to follow to connect those models.=20 On the memory side we are going to use SODIMM=E2=80=99s and we got the EBD = and IBIS models for those DIMM=E2=80=99s from our supplier.=20 I have tried to do some pre-layout simulations in LineSim using the models = provided and on a very simple point to point DQ topology I got a very ugly = signal at the DIMMs, which seem to be determined by a huge attenuation intr= oduced by the package parasitic, so I decided to validate my model before t= o investigate the spice models.=20 From the IBIS model I determined that Vref =3D1.5V, Rref =3D50Ohms and Cref= =3D0. Many documents I have read are suggesting that the test load would be= in this case a simple pull-up resistor connected to a 1.5V power rail. I d= id try and the results of simulation are showing a DC offset, so the Vol DC= =3D600mV > Vil DC=3D595Mv, which tells me that the test circuit isn=E2=80= =99t the right one. If I replace the Vref with 0.75V the output signal make= s sense.=20 The questions that arise are:=20 =E2=80=A2Are the Vref, Rref and Cref the parameters describing the test loa= d? =E2=80=A2If yes, this holds true even if the IBIS model is actually the mod= el of the die? =E2=80=A2If we add to the IBIS models the series Spice parasitic models the= test load will still be described by those parameters? =E2=80=A2What would be the best way of using this combination of IBIS-HSPIC= E models in LineSim and BoardSim? =E2=80=A2It is possible to run batch mode simulation in BoardSim using this= combination of models? =E2=80=A2If in top of those we add some timing models what would be the com= bined solution to do SI and timing analysis? =E2=80=A2It is ICX or ICX Pro (Explorer and Verify) more suitable for this = kind of situation? Thank you in advance, Cristian Filip =0A=0A=0A ____________________________________________________________= ______=0AYahoo! Canada Toolbar: Search from anywhere on the web, and bookma= rk your favourite sites. Download it now at=0Ahttp://ca.toolbar.yahoo.com. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu