[SI-LIST] Buried capacitance layer; ? Area to use? Use with discrete caps?
- From: "tom_cip_11551" <tom_cip_11551@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 03 Jun 2008 21:27:43 -0000
Hi Si-List PCB design experts.
If I had a large buried capacitance layer, a vcc and ground, and stuck
a single part in the center of it requiring decoupling, how much
capacitance would the vcc pin of the part actually "see"? Is this a
distributed capacitance? I know that they say to use a rule of thumb
like 500 pF/in2. But for each square inch of buried capacitance that I
use does the sum add linearly?
In my case, I am considering using a buried capacitanc layer in a pcb
where the switching is done at 4Gb/s. I have several circuits that are
identical but not running on the same supply, so the area of buried
capacitance will not be all that large.
My original concept is to use a small section of buried plane for high
speed switching and have some larger decoupling caps (.01 uF 402)
connected through vias to make up for what the plane can not handle at
lower frequencies. Now if I use, say, a square inch of buried plane per
device, that would amound to something like 500 pf of plane capacitance
and .01 uF of discrete. Generally speaking, is this too small of a
buried capacitance to use?
Finally, I have read that using discrete caps and buried capacitance
can give more problems with respect to EMI than using each alone. Is
this true?
Thank you to all who respond.
Tom
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