[SI-LIST] cPCI backplane signal traces - characteristic impedance
- From: "Sexton, Brian M. \(US SSA\)" <brian.m.sexton@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 23 Jun 2008 15:13:44 -0400
In reading the PCI specification for 66MHz cPCI backplanes, it states
one should use 65 ohms for the bussed signals. I believe that COTS
backplanes use a recipe like this with traditional strip-line
construction. It also states the 66MHz backplanes should be 5 slots or
less.
=20
We need to design a 5-slot cPCI rigid-flex-rigid backplane which also
includes routing for lots of 100 ohm differential I/O pairs. It is only
the I/O that crosses the flex. The cPCI section is the traditional 0.8"
pitch using the normal hard metric connectors in one of the rigid
sections. =20
=20
My problem is that it takes (4) double sided flex layers for all the I/O
signals that cross between the hard boards. At 5 mils dielectric per
flex, it is almost impossible to make the 65 ohms on those layers. If I
use a traditional 65 ohm stripline for the PCI signals, and only use the
flex layers for the I/O, my backplane will be greater than 0.200" thick.
=20
My question is how well a 66HMz cPCI would work running the signals at
50 ohms. Does anyone have any experience with this? I'm not sure how
much margin is in the 65 recipe in the spec, and I don't have good
models for the connectors and such to trust a simulation.
=20
My only other idea was to stackup the PCI area differently than the rest
of the backplane and essentially make them asymmetrical striplines using
a plane-void-signal-plane, where the I/O would be more of a plane-signal
plane stackup. No signals would need to cross a stack up change.
However, some people have been worried about the manufacturing yield of
doing it.
Thanks for your help.
Brian
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