[SI-LIST] Re: Does anyone use "buried capacitance" layers?

  • From: "Riley, Andrew" <andrew.riley@xxxxxxxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 25 Jun 2008 11:11:59 -0700

Tom,

Twenty three licensed fabricators if I counted the dots in the PDF
correctly.=20
http://www.sanmina-sci.com/Solutions/pdfs/pcbres/BC%20Licensed_fab.pdf

Cheers!
Drew
=20
Andrew W. Riley III
Senior Designer
EADS North America Defense Test & Services
Irvine, CA.  92618

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Bill Wurst
Sent: Wednesday, June 25, 2008 10:34 AM
To: tom_cip_11551
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Does anyone use "buried capacitance" layers?

Tom,

An alternative to the Sanmina IP is C-Ply by 3M (see:
        (http://tinyurl.com/4bw9oc)
and look for the Embedded Capacitor Material link at the bottom of the=20
page).  This material can be used for either buried or embedded=20
applications.  If you want a contact at 3M call or email:
        Joel Peiffer
        jspeiffer@xxxxxxx
        651-575-1464

Two companies that have experience fabricating boards using this=20
material are:
        Endicott Interconnect:
                (http://www.eitny.com/)
and
        Compunetics:
                (http://www.compunetics.com/)
I'm know there are others.

I don't believe it is widely used as it drives the cost of the boards up

(from both material & yield perspective - the cost impact will depend on

your application).  However, it is a viable technology.  Istvan Novak=20
has written extensively on its use and advantages.

Best regards,
     -Bill

       /************************************
      /      William C. Wurst, PE         /
     /        billw@xxxxxxxxxxx          /
    / Advanced Electronic Concepts, LLC /
   /           www.aec-lab.com         /
   ************************************
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
tom_cip_11551 wrote:
> Hi,
>=20
> I first heard about buried capacitance (not to be confused with=20
> embedded capacitance) for power and ground, using thin dialiectrics,=20
> over 10 years ago, from the original papers that Hadco had published.=20
> I had thought that since the technology has been around for so long=20
> that most fab houses would be able to use it.
> =20
> I figured that my latest PCB, that is running signals at over 3 Gb/s,=20
> and has some limitations in terms of space for decoupling caps, would=20
> be a good candidate for a bured capacitance layer (two layers and a 2=20
> mil dialectric core). When I sent the board out for quote I was=20
> surprised to learn that only Sandmina Circuits "owns" the technology=20
> and very few other vendors have licensed it.
>=20
> So, I would like to know from the SI community at large, if this=20
> technology is widely used. If so, could I get the name of some=20
> alternate vendors that have licensed it?
>=20
> Also, what is the general consenus of the viability of buried=20
> capacitance (not embedded capacitance).
>=20
> Thank You
> Tom
> tom_cip_11551@xxxxxxxxxxx
>=20
>=20
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