[SI-LIST] Re: Does anyone use "buried capacitance" layers?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: tom_cip_11551 <tom_cip_11551@xxxxxxxxx>
- Date: Wed, 25 Jun 2008 11:49:53 -0700
Tom, thin dielectric has long been used for performance advantages in
the industry. Sanmina/SCI has inherited the Zycon / Hadco patents.
DuPont and Oak-Mitsui both have licenses where Sanmina/SCI gets their
money from the material supplier. As an end user you don't have to take
out a license. The materials offered by the various vendors at 1mil
differ, so you should speak to each supplier and decide which material
you prefer. We have a consulting relationship with DuPont. We have
also used Oak-Mitsui down to 12um with great success. There is no
shortage of PCB fab houses that can handle 1mil materials. But "Bob's
Backwater House of Ribs and PCB Fab" won't do.
2mil material has been used in high performance products for years.
Virtually all the big name OEM vendors are either using 1mil material
today or are looking at it very carefully. This has been accelerated by
recent price drops in the material that make 1mil not just attractive
for high performance, but actually for cost savings as well.
There are three key things that you get from thin dielectric:
* Below the Fco between the bypass network and the bypass caps the
spreading inductance is reduced. This lets you reduce the number of
bypass caps needed to support any given IC.
* Above Fco the impedance of thin dielectric is lower than thick dielectric.
* Thin dielectric has lower Q at modal resonances than thick dielectric.
For a SERDES application, depending on the : areal size of the cavity,
the IC attach pattern, the cavity thickness, the material eR, target
impedance and operating bit rate, the discrete bypass network still has
a big impact on jitter performance. X2Y(r) has demonstrated with 100um
cavities dramatic improvement ( >33% ) jitter reduction on 3.125Gbps
links. We also managed to do this while chopping down the number of
bypass caps by more than 3:1. Substantial improvement would still carry
to 25um cavities of the same geometry and eR. So, if you want to
dramatically drop your capacitor count on the order of 7:1 or even 10:1
or more and get the best possible performance, combining 1mil dielectric
with X2Y(r) caps is a killer solution.
Steve.
tom_cip_11551 wrote:
> Hi,
>
> I first heard about buried capacitance (not to be confused with
> embedded capacitance) for power and ground, using thin dialiectrics,
> over 10 years ago, from the original papers that Hadco had published.
> I had thought that since the technology has been around for so long
> that most fab houses would be able to use it.
>
> I figured that my latest PCB, that is running signals at over 3 Gb/s,
> and has some limitations in terms of space for decoupling caps, would
> be a good candidate for a bured capacitance layer (two layers and a 2
> mil dialectric core). When I sent the board out for quote I was
> surprised to learn that only Sandmina Circuits "owns" the technology
> and very few other vendors have licensed it.
>
> So, I would like to know from the SI community at large, if this
> technology is widely used. If so, could I get the name of some
> alternate vendors that have licensed it?
>
> Also, what is the general consenus of the viability of buried
> capacitance (not embedded capacitance).
>
> Thank You
> Tom
> tom_cip_11551@xxxxxxxxxxx
>
>
>
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