[SI-LIST] Re: How to calculate/obtain footprint ind/cap characteristic for 402, 603, etc?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: tom_cip_11551 <tom_cip_11551@xxxxxxxxx>
- Date: Thu, 05 Jun 2008 16:53:23 -0700
Tom, I see Scott has already answered this.
In order to avoid turning every design into a college thesis, the best
that I can recommend is that you rigidly adhere to a fixed mount / via
design for your capacitors. The next problem to overcome is variation
in the distance from the capacitor mounting surface to the first RF
plane in the PCB. As you will find in our papers depending on just how
accurate you need to be, you can zero this out provided that it isn't
more than about 15 mils into the board. The remaining problems will be
those of variation from mfg to mfg, and cover layer which tends to grow
for a particular capacitor value over time. What happens is that as the
MLCC manufacturers get better and better at making thinner and thinner
plates, they use fewer plates for a given capacitor value. They build
the plates out from the middle, so the cover layer gets thicker over
time increasing mounted inductance. Today's 2uF capacitor that fully
packs a capacitor to within a couple of mils of the outer surface will
become next year's capacitor with a cover layer nearly twice as thick.
If you are doing everything right: power cavity close to the surface,
good capacitor mount and via design, etc then the cover layer variations
can have a visible impact. If you are sloppy with things like the power
cavity far from the capacitor surface, then via inductance will swamp
out any cover layer impact.
You can get around the cover layer variation problem by remaining
conservative, which will also help your pocketbook. If you are going to
use a big Vish kind of design with only one or a few capacitor values,
instead of using the largest capacitor in a given body size as your
primary value, begin two capacitor sizes down. MLCC capacitor
manufacturers charge for Farads when the capacitors are relatively fully
packed. This has a strong influence on price for only the largest and
second largest values in a particular case size. Below that, you are
paying mostly for the shipping ( no joke! ). You can still use the
biggest values, just use them as a small proportion of your network, and
model them as though they have a thick cover layer. Because next year
they will. This will save you money, and BTW it will keep your ESR from
getting unnecessarily low which can help with resonance management. See
various papers by Larry Smith on that. If you are designing a flat
array ala Larry's FDTIM, then you will naturally only use a couple
capacitors that fill out their cases anyway.
Once you adopt these procedures, you can reasonably design your network
using fixed models and pretty much any of the tools out there from:
Ansoft, Sigrity, Cadence, etc and get reasonably good correlation from
simulation and what your design really does. Further, you won't have to
worry about constantly tracking source control and manufacturer
variations in their capacitors.
The really big issue in PDN design is getting accurate information from
your IC suppliers: What current spectrum does your PDN need to support,
and what parasitics are buried inside the IC package. If you don't have
that information, then you'll end up with a PDN design that either costs
much more than it should, or that doesn't perform as needed, or both.
Steve.
X2Y measured several capacitor package configurations with very accurate
fixtures that we developed for that purpose. You can find the results
on the X2Y website in the decoupling section. One of the papers has a
summary chart that shows mounted inductance versus cavity depth.
tom_cip_11551 wrote:
> Hi,
>
> I am trying to determine an optimum decoupling strategy. I have found
> lots of manufacturers data conerning capacitor models, from Murata and
> others. But I keep thinking that these models can't possibly take into
> consideration the layout footprint, because of process, material and
> other variations, like the layer height above copper.
>
> So, when attempting to model a capacitor in spice or other, what is a
> good strategy in trying to take into consideration the footprint itself?
>
> Yes, I do realize that in some cases, a 3D model can be created, but
> that can be very time consuming and I am really only talking about a
> first order spice approximation.
>
>
> Thank you to all who respond.
>
> Tom
>
>
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