Posts for si-list, 11-2001

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  1. » [SI-LIST] Re: Historical question: IBIS & Quad TLC?, Muranyi, Arpad
  2. » [SI-LIST] Re: Differences between HSPICE Field Solver and XTK Field Solver, Mike Ventham
  3. » [SI-LIST] Loss tangent and Dielectric conductance, Peter LaFlamme
  4. » [SI-LIST] Re: Loss tangent and Dielectric conductance, Ozgur Misman
  5. » [SI-LIST] Re: Differences between HSPICE Field Solver and XTK Field Solver, Kevin Ko
  6. » [SI-LIST] shielding effectiveness, Wani, Vijay (V)
  7. » [SI-LIST] more on glitches caught on a scope, Douglas C. Smith
  8. » [SI-LIST] Intusoft ICAP4/IsSpice vs. Cadence Capture/PSpice, Michael Bogusz
  9. » [SI-LIST] Signal integrity analysis checklist, Siva kumar
  10. » [SI-LIST] Re: Ansoft Turbo Package Analyzer, Quiobo, Erwin
  11. » [SI-LIST] New App Notes: Switching Noise, HDI, Inductance..., Gary Otonari
  12. » [SI-LIST] Impedance measurement using TDR, Bob Patel
  13. » [SI-LIST] Re: Trace Inductance, Tsuk, Michael
  14. » [SI-LIST] Re: Conductivity for FR4, Joachim Mueller
  15. » [SI-LIST] High RF impedance surfaces, Steve Rogers
  16. » [SI-LIST] Resistivity of Bras, Rich Peyton
  17. » [SI-LIST] Re: Resistivity of Bras, jrbarnes
  18. » [SI-LIST] distributed packaging model, Perry Qu
  19. » [SI-LIST] Re: distributed packaging model, Ozgur Misman
  20. » [SI-LIST] Looking for replacement tips for a Tektronix P7330 diff probe......, Greim, Michael
  21. » [SI-LIST] Impedance mismatch due to Cu pours, Shankar . Raj
  22. » [SI-LIST] Re: Impedance mismatch due to Cu pours, Nagel, Michael
  23. » [SI-LIST] emi shielding, Wani, Vijay (V)
  24. » [SI-LIST] Re: emi shielding, Wani, Vijay (V)
  25. » [SI-LIST] Re: Impedance measurement using TDR, Daniel, Erik S., Ph.D.
  26. » [SI-LIST] Are there any ways to use DSO type scopes for eye pattern measurement?, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  27. » [SI-LIST] Re: Are there any ways to use DSO type scopes for eye pattern measurement?, Zabinski, Patrick J.
  28. » [SI-LIST] Re: Are there any ways to use DSO type scopes for eye p attern measure ment?, =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
  29. » [SI-LIST] PCI-X package info., Tariq Abou-Jeyab
  30. » [SI-LIST] Question about Mixed Signal On PCB, 남성엽
  31. » [SI-LIST] [Question]Mixed Signal PCB, \xB3\xB2\xBC\xBA\xBF\xB1
  32. » [SI-LIST] [Question]Mixed Singal PCB ground strategy, \xB3\xB2\xBC\xBA\xBF\xB1
  33. » [SI-LIST] Re: PCI-X package info., Ingraham, Andrew
  34. » [SI-LIST] PCI-66 design rules, KOK TONG THAM
  35. » [SI-LIST] Re: PCI-66 design rules, Ingraham, Andrew
  36. » [SI-LIST] Quarter wavelength transmission lines, richard hill
  37. » [SI-LIST] Re: Quarter wavelength transmission lines, jrbarnes
  38. » [SI-LIST] PCB design and manufacturing magazines, Alex March
  39. » [SI-LIST] Re: PCB design and manufacturing magazines, Kai Keskinen
  40. » [SI-LIST] Interconnect Synthesis, Juan Manuel
  41. » [SI-LIST] Re: RF layout guidelines, Javier del Valle
  42. » [SI-LIST] Paksi-E in BGA Substrate Design?, Erhan Kaya
  43. » [SI-LIST] Er Variation, Martyn Gaudion
  44. » [SI-LIST] LVPECL DC bias, Lianghu Xu
  45. » [SI-LIST] Test point program., Inmyung Song
  46. » [SI-LIST] Common Mode choke coil -Spice Model, Suresh Sivasubramaniam
  47. » [SI-LIST] AW: Common Mode choke coil -Spice Model, Neibig Uwe (GS/EDK) *
  48. » [SI-LIST] S-parameter simulation in Time Domain, Larry Smith
  49. » [SI-LIST] Re: S-parameter simulation in Time Domain, samir_aboulhouda
  50. » [SI-LIST] Re: Common Mode choke coil -Spice Model, Ray Anderson
  51. » [SI-LIST] Recent VIrus 'postings', David Instone
  52. » [SI-LIST] trellis coding, Rengarajan S Krishnan
  53. » [SI-LIST] Re: Recent VIrus 'postings', Ray Anderson
  54. » [SI-LIST] Re: Fw: Re: S-parameter simulation in Time Domain, Steve Corey
  55. » [SI-LIST] Help in interpreting this hspice command, mvvijay
  56. » [SI-LIST] Position wanted in Italy, David Instone
  57. » [SI-LIST] Inductance of Spiral Inductors, Rafael Martinez
  58. » [SI-LIST] Re: Inductance of Spiral Inductors, Dan Swanson
  59. » [SI-LIST] test *eom*, Vadim Heyfitch
  60. » [SI-LIST] Bit Error Caused by NOISE, Lianghu Xu
  61. » [SI-LIST] Re: Bit Error Caused by NOISE, Zabinski, Patrick J.
  62. » [SI-LIST] Re: Inductance of Spiral Inductors - why not to use a network analyser for Q measurement, Steve Rogers
  63. » [SI-LIST] Stackup layer change - effect on partial self inductance of the plane, Chowdhury, Musawir M (Musawir)
  64. » [SI-LIST] Re: Stackup layer change - effect on partial self inductance of the plane, Chowdhury, Musawir M (Musawir)
  65. » [SI-LIST] Re: Stackup layer change - effect on partial self inductance of the p lane, Erhan Kaya
  66. » [SI-LIST] Differential Impedance, Erhan Kaya
  67. » [SI-LIST] replacing ECL ??, Robison Michael R CNIN
  68. » [SI-LIST] offset, Steve Gonzales
  69. » [SI-LIST] Re: replacing ECL ??, Greim, Michael
  70. » [SI-LIST] Power handling, Hassan Ali
  71. » [SI-LIST] Re: Power handling, Michael Nudelman
  72. » [SI-LIST] Re: Square wave harmonics, Michael Nudelman
  73. » [SI-LIST] Yeee-Ha!, D. C. Sessions
  74. » [SI-LIST] physics behind EMI powerline filters, Muriel Bittencourt de Liz
  75. » [SI-LIST] Sanmina patent on dielectric thicknesses under 4 mils, Ron Miller
  76. » [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mils, Zabinski, Patrick J.
  77. » [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mi ls, Moran, Brian P
  78. » [SI-LIST] Re: Sanmina patent on dielectric thicknesses under 4 mi ls, Khederian, Bob
  79. » [SI-LIST] Using XFX Field Solver, tcoyle
  80. » [SI-LIST] FW: Re: Sanmina patent on dielectric thicknesses under 4 mi ls, Chris Cheng
  81. » [SI-LIST] Re: FW: Re: Sanmina patent on dielectric thicknesses under 4 mi ls, Chris Cheng
  82. » [SI-LIST] Re: Si-list is one awesome avenue to learn and contribute to Signal Integrity, Grossman, Brett
  83. » [SI-LIST] Re: Si-list is one awesome avenue to learn and contribute to Signal Integrity, Tsuk, Michael
  84. » [SI-LIST] Buried Capacitance thread comments, MikonCons
  85. » [SI-LIST] Buried Capacitance thread comments (The whole thing), MikonCons
  86. » [SI-LIST] Re: Buried Capacitance thread comments (The whole thing), Chris Cheng
  87. » [SI-LIST] Swing control for Gigabit chips, Alex March
  88. » [SI-LIST] Re: Swing control for Gigabit chips, Bill . Cohen
  89. » [SI-LIST] Re: Buried Capacitance thread comments (The whole thing ), Ray Anderson
  90. » [SI-LIST] PCD Mag article on PDS design, Eric Bogatin
  91. » [SI-LIST] public domain 2D RLGC solver, Marc McDougall
  92. » [SI-LIST] Re: public domain 2D RLGC solver, Jason Miller
  93. » [SI-LIST] Re: lumped model vs distributed model, Jason D Leung
  94. » [SI-LIST] Update on information requested on Buried Capacitance etc.., Charles Grasso
  95. » [SI-LIST] multi-band devices, Wani, Vijay (V)
  96. » [SI-LIST] Trace spacing between 200 MHz signals, richard hill