[SI-LIST] Stackup layer change - effect on partial self inductance of the plane
- From: "Chowdhury, Musawir M (Musawir)" <musawir@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 21 Nov 2001 13:35:18 -0500
All:
Having a problem on the Flipchip package substrate layer stackup to lower
the utility plane inductance.
The original design stackup
-------- bump pad, VSS1 (interested in the partial inductance of this plane)
-------- signal
-------- VDD1, VSS1 (small VSS1 plane connected to the VSS1 bump pads on
layer 1 and connected back to VSS1 on layer 1 and layer 7)
-------- VSS
-------- VDD1
------- signal
------- BGA pad, VSS1
The modified design stackup
-------- bump pad, VDD1 (interested in the partial inductance of this plane)
-------- signal
-------- VSS1
-------- VSS
-------- VDD1
------- signal
------- BGA pad, VSS1
We expected the partial inductance of the VSS1 plane in the modified design
stackup to have lower value. But it turned out to be higher than the
original design. We used PAKSI-E tool to extract the partial inductances.
This tool takes the gerbers as the input files. There was no input violation
and the tool was consistent in providing reasonable results in other
designs.
Can anybody help me understand why the inductance is higher in the modified
design.
Thanks in advance for any help,
Musawir
___________________________________________________________
Musawir Chowdhury musawir@xxxxxxxxx
agere systems Tel: 610-712-8175
Packaging & Interconnect Technology Fax: 610-712-5818
Design Integration
Allentown, PA
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