[SI-LIST] Re: Buried Capacitance thread comments (The whole thing)
- From: "Istvan Novak" <istvan.novak@xxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Nov 2001 09:01:26 -0500
Hi,
Seeing the (still) high interest on the subject, let me offer my brief
personal opinion:
- as various claims indicate, good real-life designs can be achieved with or
without thin laminates (or 'buried capacitance')
The design procedure with thin laminates should make proper use of the thin
laminates, otherwise the thin laminate is just extra cost. Designs without
thin laminates should make sure that a) fast core and signal transients are
limited by system design measures or properly trapped (e.g., with package
capacitors) and the stackup/via transitions are done accordingly, b) plane
resonances are suppressed or are not excited (signal bandwidth is lower than
the lowest resonance) or for any reason the resonances do not matter
(possible long list)
- 2-mil BC laminate by itself does not eliminate resonances; only <0.3-mil
laminate thickness and/or a loss tangent >0.3 would do
- via stitching, hundreds/thousands of capacitors and packages/silicons do
change the resonance pattern, but by default those still do not eliminate
resonances (but as said they may not matter)
At DesignCon2002 (1/28/02, Santa Clara, CA) the HP-TF2 TecForum
(http://www.designcon.com/2002/hp_m9am.html#hp-tf2) is:
"Thin PCB Laminates for Power Distribution: How Thin is Thin Enough?"
The presenting companies: StorageTek, AMD, Compaq, SUN, Nortel, Aromat,
DuPont, 3M, Sanmina, Merix, Wus.
regards
Istvan Novak
SUN Microsystems
----- Original Message -----
From: "Scott McMorrow" <scott@xxxxxxxxxxxxxxxx>
To: <chris.cheng@xxxxxxxxxxxx>
Cc: <MikonCons@xxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Thursday, November 29, 2001 4:02 AM
Subject: [SI-LIST] Re: Buried Capacitance thread comments (The whole thing)
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>
> As the Irishman said:
>
> "Is this a private fight, or can anyone join?"
>
>
> Chris Cheng wrote:
>
> > There are those who use scare tactics to justify their consulting
> > jobs and academic life and there are those who have to do real
> > designs and ship products.
>
> Yes, and I believe Mike has a track record of many successful
> designs and products shipped over many years.
>
> > What the paper didn't say is if you bury the signal trace with
> > the proper reference planes and there by providing the lowest
> > and tightest coupling return path, the EMI and noise will drop
> > to beyond any 100's of caps or Zycon plane can provide you.
>
> This is only correct if the same was done on the device at the
> package. (i.e. the signal is launched from the die onto stripline
> sandwiched between symmetric I/O power and ground planes,
> or proper return path structures.) Unfortunately, most devices
> are not packaged in such a way. The signal launch is generally
> referenced primarily to one plane or the other.
>
> In the case of an asymmetric launch, a mode has already been
> established between the signaling conductor and one or more
> reference conductors. The best a board designer can do at
> this point is to maintain the same return path mode on transition
> from the package to the board. In this way, mode conversion will
> not occur, or be minimized. It is mode conversion that launches
> energy into the power and ground plates at the transition from the
> package to the board.
>
> Chris, you assume a purely symmetric return path at the die launch.
> This is not usually the case, unless specifically designed that way.
> I do agree that this would be the ideal, however impractical it might
> be for most designs, due to the added cost of multiple layer buildup
packages.
> For the highest performance designs one must try to keep the signal
> return path continuous from package to board. It is key to remember
> that the signal return path is not necessarily the same as the power
> return path. In a perfect world, both would be the same. Once the
> signal has been launched on a waveguide structure, and the fields
> have "adjusted" themselves to this condition, the wave does not care
> what potential the underlying guiding structure is at (power, ground or
> even floating.)
>
> It is the transition that is important, nothing more. For a
> single ended I/O signal, the first transition which occurs is at the
> die/substrate boundary. If the transition is asymmetric, as it often
> is, then some of the energy mode converts to the proper stripline or
> microstrip mode onto the substrate trace, and the remainder of the
> energy mode converts to one of many power distribution modes (which
> depend on the package and die design.) It is this first mode conversion
> at the die where a substantial amount of "power" noise is developed, and
> is due to imperfect substrate design. Much of system noise has it's
> origins here.
>
> The next mode conversion that occurs will be in the necessary via
> transitions on the substrate as the signal winds it's way down to the
> ball layer. Mode conversions here will launch energy from the via
> stack into the power and ground plate modes (assuming that power
> and ground planes actually exist in a particular package). This, again,
> is totally dependent upon the design of the substrate and ball out
> pattern. The ball (and via) pattern in the region of a particular
> signal escape should attempt to maintain a continuous return path
> from the substrate through to the board. (i.e. if the substrate signal
> is mostly referenced to ground, then the neighboring vias and balls
> should be referenced to ground. If the signal is mostly referenced to
> a particular power plane, then the neighboring vias and balls should
> be referenced to that same power rail.
>
> (The above can be quite easily verifed using full wave FDTD or
> frequency domain solvers.)
>
> If a designer has detailed knowledge regarding the package routing
> and signaling reference for each signal, then an optimal PCB (or MCM)
> routing solution can be generated that maintains the same launch
> reference across the Package/Ball/Board interface. ( For example, if the
signal is
> referenced to ground, then it should be referenced to ground at the
> board to reduce mode conversion, noise and EMI.)
>
> Since most mortal designers do not have access to detailed knowledge
> regarding the package routing and signaling reference for each signal,
> a compromise solution is possible. What you talk about (incessantly)
> Chris, is really just that, a "rule of thumb" compromise solution that
> works well in all systems. That is, to route all PCB signals as stripline
> between an I/O power plane and a ground plane. In fact, what I believe
> you advocate is this structure.
>
> -------------------- ground
> -------------------- power
> ---- signal
> -------------------- ground
> -------------------- power
>
> This is the best possible compromise PCB signal routing geometry, when
> the designer does not have enough information to actually engineer the
> correct structure, due to limitations in the packages or knowledge
thereof.
> It is, however, quite inefficient in terms of z-axis space utilization.
And the
> method falls apart if a designer cares to utilize dual asymmetric
stripline
> layers to reduce overall layer count and cost.
>
> For any signal that is launched from a package to a board, with a power
and
> a ground plane, there are three possible basic signal/power waveguide
> modalities that can occur. 1) the signal is stripline and is between a
power and
> a ground plane. 2) the signal is microstrip or stripline and is
referenced to
> only a power plane. 3) the signal is a microstrip or stripline and is
referenced
> to only a ground plane. (Actually, there are several others which we will
neglect
> for this discussion.)
>
> Now, assuming that the package waveguide modality was maintained through
> the the package vias and ballout, the "Chris Chang" method of signal
routing
> is optimal for only case number 1, where the signal is referenced to a
power and
> a ground plane. Here this mode can be continued from the package through
> to the board without mode conversion occuring. For cases 2 and 3, Chris'
> method is not optimal. For example, a power plane referenced signal will
> need to mode convert at the transition to properly attach to the ground
plane
> of the PCB waveguide structure. For case 2, the perfect PCB structure
would
> be power referenced microstrip or stripline (between two power planes).
For case 3,
> the perfect PCB structure would be ground referenced stripline or
microstrip.
>
> For cases 2 and 3, the mode conversion is handled by local power/ground
plane
> pairs on either side of the stripline. This high quality distributed low
impedance
> LC circuit quickly provides closure of the return path, facilitating
minimal distruption
> during conversion to the proper stripline mode. Noise is created on the
power
> and ground planes when the mode conversion occurs. This noise will never
> be less than the optimal structure which maintains the same mode across
the
> entire board from package to package.
>
> > Sprinkle in hundreds of decoupling
> > capacitors with different values and in different location.
> > Then put in thousands of power and ground vias mimicking
> > real life package power and ground pins. Stitch ground
> > vias around the edge of the board like what real world
> > design. Lets see if you still have your resonance.
> >
>
> Absolutely. All parallel plate waveguides resonate. It is just a matter
> of the interactions of all the structures involved (planes, vias, splits,
> devices.) In fact, all non perfectly terminated structures have multiple
> resonant eigenmodes. Some which can have a quite high Q. It's fairly
> easy to find the resonant modes with a VNA, a spectrum analyzer, or
> with some effort with full wave board simulation software. With some of
> the new fast solver technology, we should start seeing some commercial
> solutions become available in the next few years. In that case, we will
> all be able to simulate these sorts of full board problems in minutes
instead of
> hours or days.
>
>
> regards,
>
> scott
>
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR 97062-3090
> (503) 885-1231
> http://www.siqual.com
>
>
>
> >
> > -----Original Message-----
> > From: MikonCons@xxxxxxx [mailto:MikonCons@xxxxxxx]
> > Sent: Wednesday, November 28, 2001 6:38 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Buried Capacitance thread comments (The whole thing)
> >
> > [MLC] Sorry, Chris, but you are WAY off on this one. Check out the
> > literature
> > from 1989-1991 and the electronic "Product of the Year" award given to
Zycon
> >
> > for the ZBC 2000 product (the original name) for EMI reduction. I know
you
> > are practicing some good design to achieve Class B certification, but
good
> > power/ground plane decoupling plays a major part in that success. Many
> > papers
> > demonstrated attenuatin of 20-30 dB over all frequencies above 40 MHz
when
> > using BC and DELETING over 100 0.1 Uf decoupling capacitors. (Check with
Dr.
> >
> > Jim Howard at Sanmina, Santa Clara, CA if you doubt this.) Lee Ritchey
> > commented correctly on the contribution of the planar decoupling.
> > *********
> > [MLC] Chris makes a key point in identifying the return path for any
> > high-speed currents. However, the reference to the Zycon planes seems to
be
> > a
> > slam at the benefits of that technology. If one studies RF techniques in
> > depth, then the fact that for a given resonance frequency the Q of that
> > resonance
> > is decreased with increased capacitance. This is the unheralded forte of
the
> >
> > buried capacitance concept. I have performed spectrum analyzer tests
(with a
> >
> > tracking generator) on circular and square PCBs (11" diameter/side)
> > employing
> > BC that clearly demonstrated (relative to identical PCBs without BC) NO
> > RESONANCE effects at high frequencies (>40 MHz). The effect of this
> > characteristic is LOWER EMI that is (many times) caused by PCB
dimensional
> > resonances. This benefit is particularly useful for High-Tg FR-4 boards
and
> > higher frequency designs (>500 MHz) as the FR-4 losses play a
significant
> > role at the higher harmonics.
> > *********
> > >From the above comnments, I wish only to convey that we are all still
> > learning, and an open mind is critical to solving the design challenges
of
> > the future.
> >
> > Mike
> >
> > Michael L. Conn
> > Owner/Principal Consultant
> >
> > Mikon Consulting
> >
> > *** Serving Your Needs with Technical Excellence ***
> >
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