[SI-LIST] Re: Stackup layer change - effect on partial self inductance of the plane
- From: "Chowdhury, Musawir M (Musawir)" <musawir@xxxxxxxxx>
- To: "'jpowell@xxxxxxxxxxxx'" <jpowell@xxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Wed, 21 Nov 2001 21:56:54 -0500
Jon:
Thanks for the response. It's a 7 metal layer stack-up of 12um Cu,
dielectric height being 58um between the metal planes. You can consider the
effective dielectric height to be 48um between the signal plane and the
utility plane on that side.
Regards,
Musawir
-----Original Message-----
From: Jon Powell [mailto:jpowell@xxxxxxxxxxxx]
Sent: Wednesday, November 21, 2001 1:31 PM
To: musawir@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Cc: 'Tatikola, Ramani (Ramani)'
Subject: RE: [SI-LIST] Stackup layer change - effect on partial self
inductance of the plane
Inductance implies loop area. Which in similar lay-out usually means a
difference in the thickness of the materials. You didn't provide stack-up
heights.
jon powell
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chowdhury, Musawir M
> (Musawir)
> Sent: Wednesday, November 21, 2001 10:35 AM
> To: 'si-list@xxxxxxxxxxxxx'
> Cc: Chowdhury, Musawir M (Musawir); Tatikola, Ramani (Ramani)
> Subject: [SI-LIST] Stackup layer change - effect on partial self
> inductance of the plane
>
>
>
> All:
>
> Having a problem on the Flipchip package substrate layer
> stackup to lower
> the utility plane inductance.
>
> The original design stackup
>
> -------- bump pad, VSS1 (interested in the partial inductance
> of this plane)
> -------- signal
> -------- VDD1, VSS1 (small VSS1 plane connected to the VSS1
> bump pads on
> layer 1 and connected back to VSS1 on layer 1 and layer 7)
> -------- VSS
> -------- VDD1
> ------- signal
> ------- BGA pad, VSS1
>
>
> The modified design stackup
>
> -------- bump pad, VDD1 (interested in the partial inductance
> of this plane)
> -------- signal
> -------- VSS1
> -------- VSS
> -------- VDD1
> ------- signal
> ------- BGA pad, VSS1
>
>
> We expected the partial inductance of the VSS1 plane in the
> modified design
> stackup to have lower value. But it turned out to be higher than the
> original design. We used PAKSI-E tool to extract the partial
> inductances.
> This tool takes the gerbers as the input files. There was no
> input violation
> and the tool was consistent in providing reasonable results in other
> designs.
>
> Can anybody help me understand why the inductance is higher
> in the modified
> design.
>
> Thanks in advance for any help,
> Musawir
>
> ___________________________________________________________
> Musawir Chowdhury musawir@xxxxxxxxx
> agere systems Tel: 610-712-8175
> Packaging & Interconnect Technology Fax: 610-712-5818
> Design Integration
> Allentown, PA
>
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