[SI-LIST] Impedance mismatch due to Cu pours
- From: Shankar.Raj@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 9 Nov 2001 12:11:45 +0530
Hi,
I am designing an 8 layer stackup. Due to routing requirements, atleast 4 signal
layers are needed.
Signal layers in top and bottom reduces available routing space, considering the
high density routing.
So the following stackup was considered,
P(split) - S - GND - S - S - GND - S - P(split)
The Signal layers S2 and and S7 are closer to GND planes and hence reference the
same (i.e. wrt return currents).
But I am curious to know the effect of the Split planes(1 & 8).
Does copper pours on top and bottom of board cause impedance mismatch whenever
signals in adjacent layer cross its border?
Also are return currents for S2 and S7 degraded in this stackup?
It will be helpful if someone can pass comments on the following stackup too!
GND - S - P(split) - S - S - P(split) - S - GND
Thanks and Regards,
Shankar V
FORCE Computers
Bangalore
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