[SI-LIST] Re: Impedance mismatch due to Cu pours
- From: Alan Hilton-Nickel <ahilton@xxxxxxxxxxxxx>
- To: Shankar.Raj@xxxxxxxxxx
- Date: Fri, 09 Nov 2001 06:49:51 -0800
Hi Shankar,
I have been dubious of the value of power or ground planes on outer
layers since trying to apply that approach on my last job. The problem
is this: the outer layers are also used to place components, so the pads
and breakout traces interfere with the continuity of the power/gnd
plane. EMI is better reduced through a good return path than trying to
use ground (or power) as a shield, and the voids in the plane around the
components would only increase the signal and return path inductances,
degrading your signal integrity.
If you are going to eight layers anyway, I suggest the following
stackup:
1. Top (signal 1)
2. GND 1
3. Split Power 1
4. Signal 2
5. Signal 3
6. Split Power 2
7. GND 2
8. Bottom (signal 4)
When you have the board fabricated, ask your vendor to make the distance
between the Power and Ground pairs as small as possible - 3-4 mils
should be possible, but 5 or 6 mils is probably OK (depending on your
edge rates). The resulting interplane capacitance will provide a return
path for signals routed across the split power. You'll probably want to
add extra power and ground vias in strategic places on the board to
ensure there are adequate return paths for all high-speed signals.
BTW the interplane capacitance will also reduce (not eliminate) the need
for decoupling capacitors.
Good luck,
Alan Hilton-Nickel
Transmeta Corp
Santa Clara, CA
Shankar.Raj@xxxxxxxxxx wrote:
>
> Hi,
>
> I am designing an 8 layer stackup. Due to routing requirements, atleast 4
> signal
> layers are needed.
> Signal layers in top and bottom reduces available routing space, considering
> the
> high density routing.
> So the following stackup was considered,
>
> P(split) - S - GND - S - S - GND - S - P(split)
>
> The Signal layers S2 and and S7 are closer to GND planes and hence reference
> the
> same (i.e. wrt return currents).
> But I am curious to know the effect of the Split planes(1 & 8).
> Does copper pours on top and bottom of board cause impedance mismatch whenever
> signals in adjacent layer cross its border?
> Also are return currents for S2 and S7 degraded in this stackup?
>
> It will be helpful if someone can pass comments on the following stackup too!
>
> GND - S - P(split) - S - S - P(split) - S - GND
>
> Thanks and Regards,
> Shankar V
> FORCE Computers
> Bangalore
>
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