Scott old pal, this is neither a fight, non am I Irish. You make some good reference on the imperfect nature of image current return. Lets take a closer look. As performance increases, people use different techniques to address this issue. In the not so distant past, open drain (like GTL) or emitter follower (like PECL or ECL) I/Os are used and they are by design asymmetric I/O that only need a single reference plane for current return to the driver (the other direction is being taken cared by the decoupling at the terminator) In the case of GTL, all the return path needs to reference is ground (Bill Gunning used to joke with me saying "don't call this Gunning transceiver logic, call it ground transceiver logic). Similar argument for PECL or ECL I/O's. In lots of new high speed designs differential signals are use in which they reference to themselves (in differential mode) and asymmetrical reference to the terminating voltage (common mode). From the above, asymmetric I/O is more popular than you think, but we still have to address the push pull drivers. It turns out in order to sustain the sharp edge rate even to come out of the package, a lot of those I/O uses on die decoupling to support the initial di/dt. As such they can (while "not desire" as you like to say) take return current asymmetrically, either from the ground or the i/o power through the on die decoupling. Most likely they will take the ground path for the return. As you mentioned, a lot of packages have to use microstrip to route the signals out. However, the so call mode conversion will happen at the die level through the on die decoupling such that once it comes out of the die, only ground reference is need for both transition image current to return. In that situation, either case 1) or 3) in your description will be just fine for the I/O. You can even project to case 2) is ok provided the power plane is the I/O power and the package reference planes is either power or sandwich between power and ground. What you didn't mention is what I consider case 2b) where the reference power plane is not even the I/O power e.g. the other power plane at a different level. In this situation, your mode conversion or image current return is broken. This is where people see EMI noise or signal power/ground bounce. This is when people bring in those EMI or SI consultants where they start to sprinkle in those 100's of pf decoupling caps or Zycon planes to provide the low impedance path for the image current to return. In my opinion, two wrongs doesn't equal to one right. The problem should be solved by properly referencing the signal return power/ground planes. There is another case 1b) which the power plane in the power/ground stripline is not the I/O power but other power. In this case the image current in the power plane has to return through the plane capacitance between the power/ground planes. Unfortunately, the spacing of the planes are dictated by the impedance control of the striplines and thin dielectric is just out of the question. Finally, since you know me a little bit, you should know that I used to have the luxury of 6 well trained engineers doing power analysis for me on package resonance. All the plane resonance, via location, decoupling, plane discontinuity analysis are BTDT. And guess what, the package resonance hardly goes above 100MHz and you better believe I have the best possible package design available. Any other references you came across are in the range of 10-40MHz. I have mentioned this fact many, many times in this group and those who have done the same analysis have to agree with me. Am I trying to say PCB plane don't resonance? Absolutely not. Does resonance matter above 100MHz ? Probably not. I don't quote papers, I don't just say "you are way off" without any reasons. I say what I say because I've BTDT. -----Original Message----- From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxxxxx] Sent: Thursday, November 29, 2001 1:02 AM To: chris.cheng@xxxxxxxxxxxx Cc: 'MikonCons@xxxxxxx'; si-list@xxxxxxxxxxxxx Subject: Re: [SI-LIST] Re: Buried Capacitance thread comments (The whole thing) As the Irishman said: "Is this a private fight, or can anyone join?" Chris Cheng wrote: There are those who use scare tactics to justify their consulting jobs and academic life and there are those who have to do real designs and ship products. Yes, and I believe Mike has a track record of many successful designs and products shipped over many years. What the paper didn't say is if you bury the signal trace with the proper reference planes and there by providing the lowest and tightest coupling return path, the EMI and noise will drop to beyond any 100's of caps or Zycon plane can provide you. This is only correct if the same was done on the device at the package. (i.e. the signal is launched from the die onto stripline sandwiched between symmetric I/O power and ground planes, or proper return path structures.) Unfortunately, most devices are not packaged in such a way. The signal launch is generally referenced primarily to one plane or the other. In the case of an asymmetric launch, a mode has already been established between the signaling conductor and one or more reference conductors. The best a board designer can do at this point is to maintain the same return path mode on transition from the package to the board. In this way, mode conversion will not occur, or be minimized. It is mode conversion that launches energy into the power and ground plates at the transition from the package to the board. Chris, you assume a purely symmetric return path at the die launch. This is not usually the case, unless specifically designed that way. I do agree that this would be the ideal, however impractical it might be for most designs, due to the added cost of multiple layer buildup packages. For the highest performance designs one must try to keep the signal return path continuous from package to board. It is key to remember that the signal return path is not necessarily the same as the power return path. In a perfect world, both would be the same. Once the signal has been launched on a waveguide structure, and the fields have "adjusted" themselves to this condition, the wave does not care what potential the underlying guiding structure is at (power, ground or even floating.) It is the transition that is important, nothing more. For a single ended I/O signal, the first transition which occurs is at the die/substrate boundary. If the transition is asymmetric, as it often is, then some of the energy mode converts to the proper stripline or microstrip mode onto the substrate trace, and the remainder of the energy mode converts to one of many power distribution modes (which depend on the package and die design.) It is this first mode conversion at the die where a substantial amount of "power" noise is developed, and is due to imperfect substrate design. Much of system noise has it's origins here. The next mode conversion that occurs will be in the necessary via transitions on the substrate as the signal winds it's way down to the ball layer. Mode conversions here will launch energy from the via stack into the power and ground plate modes (assuming that power and ground planes actually exist in a particular package). This, again, is totally dependent upon the design of the substrate and ball out pattern. The ball (and via) pattern in the region of a particular signal escape should attempt to maintain a continuous return path from the substrate through to the board. (i.e. if the substrate signal is mostly referenced to ground, then the neighboring vias and balls should be referenced to ground. If the signal is mostly referenced to a particular power plane, then the neighboring vias and balls should be referenced to that same power rail. (The above can be quite easily verifed using full wave FDTD or frequency domain solvers.) If a designer has detailed knowledge regarding the package routing and signaling reference for each signal, then an optimal PCB (or MCM) routing solution can be generated that maintains the same launch reference across the Package/Ball/Board interface. ( For example, if the signal is referenced to ground, then it should be referenced to ground at the board to reduce mode conversion, noise and EMI.) Since most mortal designers do not have access to detailed knowledge regarding the package routing and signaling reference for each signal, a compromise solution is possible. What you talk about (incessantly) Chris, is really just that, a "rule of thumb" compromise solution that works well in all systems. That is, to route all PCB signals as stripline between an I/O power plane and a ground plane. In fact, what I believe you advocate is this structure. -------------------- ground -------------------- power ---- signal -------------------- ground -------------------- power This is the best possible compromise PCB signal routing geometry, when the designer does not have enough information to actually engineer the correct structure, due to limitations in the packages or knowledge thereof. It is, however, quite inefficient in terms of z-axis space utilization. And the method falls apart if a designer cares to utilize dual asymmetric stripline layers to reduce overall layer count and cost. For any signal that is launched from a package to a board, with a power and a ground plane, there are three possible basic signal/power waveguide modalities that can occur. 1) the signal is stripline and is between a power and a ground plane. 2) the signal is microstrip or stripline and is referenced to only a power plane. 3) the signal is a microstrip or stripline and is referenced to only a ground plane. (Actually, there are several others which we will neglect for this discussion.) Now, assuming that the package waveguide modality was maintained through the the package vias and ballout, the "Chris Chang" method of signal routing is optimal for only case number 1, where the signal is referenced to a power and a ground plane. Here this mode can be continued from the package through to the board without mode conversion occuring. For cases 2 and 3, Chris' method is not optimal. For example, a power plane referenced signal will need to mode convert at the transition to properly attach to the ground plane of the PCB waveguide structure. For case 2, the perfect PCB structure would be power referenced microstrip or stripline (between two power planes). For case 3, the perfect PCB structure would be ground referenced stripline or microstrip. For cases 2 and 3, the mode conversion is handled by local power/ground plane pairs on either side of the stripline. This high quality distributed low impedance LC circuit quickly provides closure of the return path, facilitating minimal distruption during conversion to the proper stripline mode. Noise is created on the power and ground planes when the mode conversion occurs. This noise will never be less than the optimal structure which maintains the same mode across the entire board from package to package. Sprinkle in hundreds of decoupling capacitors with different values and in different location. Then put in thousands of power and ground vias mimicking real life package power and ground pins. Stitch ground vias around the edge of the board like what real world design. Lets see if you still have your resonance. Absolutely. All parallel plate waveguides resonate. It is just a matter of the interactions of all the structures involved (planes, vias, splits, devices.) In fact, all non perfectly terminated structures have multiple resonant eigenmodes. Some which can have a quite high Q. It's fairly easy to find the resonant modes with a VNA, a spectrum analyzer, or with some effort with full wave board simulation software. With some of the new fast solver technology, we should start seeing some commercial solutions become available in the next few years. In that case, we will all be able to simulate these sorts of full board problems in minutes instead of hours or days. regards, scott -- Scott McMorrow Principal Engineer SiQual, Signal Quality Engineering 18735 SW Boones Ferry Road Tualatin, OR 97062-3090 (503) 885-1231 http://www.siqual.com <http://www.siqual.com> -----Original Message----- From: MikonCons@xxxxxxx [ mailto:MikonCons@xxxxxxx <mailto:MikonCons@xxxxxxx> ] Sent: Wednesday, November 28, 2001 6:38 PM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Buried Capacitance thread comments (The whole thing) [MLC] Sorry, Chris, but you are WAY off on this one. Check out the literature from 1989-1991 and the electronic "Product of the Year" award given to Zycon for the ZBC 2000 product (the original name) for EMI reduction. I know you are practicing some good design to achieve Class B certification, but good power/ground plane decoupling plays a major part in that success. Many papers demonstrated attenuatin of 20-30 dB over all frequencies above 40 MHz when using BC and DELETING over 100 0.1 Uf decoupling capacitors. (Check with Dr. Jim Howard at Sanmina, Santa Clara, CA if you doubt this.) Lee Ritchey commented correctly on the contribution of the planar decoupling. ********* [MLC] Chris makes a key point in identifying the return path for any high-speed currents. However, the reference to the Zycon planes seems to be a slam at the benefits of that technology. If one studies RF techniques in depth, then the fact that for a given resonance frequency the Q of that resonance is decreased with increased capacitance. This is the unheralded forte of the buried capacitance concept. I have performed spectrum analyzer tests (with a tracking generator) on circular and square PCBs (11" diameter/side) employing BC that clearly demonstrated (relative to identical PCBs without BC) NO RESONANCE effects at high frequencies (>40 MHz). The effect of this characteristic is LOWER EMI that is (many times) caused by PCB dimensional resonances. This benefit is particularly useful for High-Tg FR-4 boards and higher frequency designs (>500 MHz) as the FR-4 losses play a significant role at the higher harmonics. ********* >From the above comnments, I wish only to convey that we are all still learning, and an open mind is critical to solving the design challenges of the future. Mike Michael L. Conn Owner/Principal Consultant Mikon Consulting *** Serving Your Needs with Technical Excellence *** ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list <//www.freelists.org/webpage/si-list> For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list <//www.freelists.org/archives/si-list> or at our remote archives: http://groups.yahoo.com/group/si-list/messages <http://groups.yahoo.com/group/si-list/messages> Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu <http://www.qsl.net/wb6tpu> ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list <//www.freelists.org/webpage/si-list> For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list <//www.freelists.org/archives/si-list> or at our remote archives: http://groups.yahoo.com/group/si-list/messages <http://groups.yahoo.com/group/si-list/messages> Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu <http://www.qsl.net/wb6tpu> ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu