Posts for si-list, 11-2004

Browse: Last Month: 10-2004 Main Archive Page Next Month: 12-2004

» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Routing multiple Audio channels -
» [SI-LIST] PCB Layer Stack up -
» [SI-LIST] Dielectric loss modeling -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Sr. level career opportunity available at Qualcomm in San Diego -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: Can a thin PCB trace be used as a reliable fuse -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: Looking for a paper -
» [SI-LIST] Re: Impedance match -
» [SI-LIST] SDRAM Blowup! -
» [SI-LIST] DDR2 SODIMMs -
» [SI-LIST] NESA moving -
» [SI-LIST] Re: Can EMI be reduced by offset clocks -
» [SI-LIST] Can EMI be reduced by offset clocks -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Impedance match -
» [SI-LIST] Looking for a paper -
» [SI-LIST] simulating bends -
» [SI-LIST] Re: About Tco -
» [SI-LIST] Re: About Tco -
» [SI-LIST] About Tco -
» [SI-LIST] Re: Battery Monitoring PCB design tradeoff... -
» [SI-LIST] Battery Monitoring PCB design tradeoff... -
» [SI-LIST] Temp change affecting PCB capacitance -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: symmetry vs length matching for diff signals -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» (no subject) -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] [Re]Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: SDRAM timing -
» [SI-LIST] Re: Transmission Line + Jitter -
» [SI-LIST] symmetry vs length matching for diff signals -
» [SI-LIST] Re: Transmission Line + Jitter -
» [SI-LIST] SDRAM timing -
» [SI-LIST] subscribe message -
» [SI-LIST] Even and odd mode xtalk for three lines -
» [SI-LIST] Re: Transmission Line + Jitter -
» [SI-LIST] Re: Transmission Line + Jitter -
» [SI-LIST] Transmission Line + Jitter -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Ansoft User -
» [SI-LIST] ragu-doubt on pull up resistance plz help -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Re: gigabit port -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: Crystal datasheet!! -
» [SI-LIST] Re: gigabit port -
» [SI-LIST] Crystal datasheet!! -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] Re: gigabit port -
» [SI-LIST] Re: gigabit port -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] gigabit port -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] Re: MicroStrip capacitance -
» [SI-LIST] MicroStrip capacitance -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Looking for Dmitri Kuznetsov -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Schematic Capture -
» [SI-LIST] Re: si-list Digest V4 #451 -
» [SI-LIST] Re: Effect of Temperature on Metal Conductivity -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Effect of Temperature on Metal Conductivity -
» [SI-LIST] Recent Graduate Looking for SI positions -
» [SI-LIST] SI openings as an intern / full time.... -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Suggestions for modeling a loaded TEM cell? -
» [SI-LIST] Re: [Bulk] Re: CML ibis model -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Job opening - San Diego - Signal Integrity Engineer 2 -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Re: CML ibis model -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Re: SI basics reference books and URL -
» [SI-LIST] Re: CML ibis model -
» [SI-LIST] CML ibis model -
» [SI-LIST] SI basics reference books and URL -
» [SI-LIST] Re: IBIS model for PCI Express Edge connector -
» [SI-LIST] IBIS model for PCI Express Edge connector -
» [SI-LIST] IBIS model for PCI Express Edge connector -
» [SI-LIST] SPI 2005 - Call For Papers -
» [SI-LIST] Re: T1/E1 Line fuse -
» [SI-LIST] Re: T1/E1 Line fuse -
» [SI-LIST] Re: PCB stack issue -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] [OT][JOB] Design Engineer -
» [SI-LIST] Re: MatLab GUI for HSPICE field solver -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: Estimate min TL spacing based on NE/FE noise budget -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: T1/E1 Line fuse -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: MatLab GUI for HSPICE field solver -
» [SI-LIST] T1/E1 Line fuse -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] FW: Estimate min TL spacing based on NE/FE noise budget -
» [SI-LIST] Does any standard mention about resistance and contact resistance measurement -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] Those of you interested in Field Solvers, Stack Ups, Spacing, Crosstalk, Matlab -
» [SI-LIST] digest on -
» [SI-LIST] Re: Estimate min TL spacing based on NE/FE noise budget -
» [SI-LIST] MatLab GUI for HSPICE field solver -
» [SI-LIST] Estimate min TL spacing based on NE/FE noise budget -
» [SI-LIST] Re: PCB stack issue -
» [SI-LIST] PCB stack issue -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: DDR1 SDRAM Termination -
» [SI-LIST] DDR1 SDRAM Termination -
» [SI-LIST] 2D simulation verification of 2wire model -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Transfer between Balance and Unbalance -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] Wishing u all a happy n joyful Deepawali !!! -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] Re: differential IBIS model generation -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] FW: Re: via-in-pad technology -
» [SI-LIST] Re: BGA routing -
» [SI-LIST] BGA routing -
» [SI-LIST] Re: Career Advice for a junior EE -
» [SI-LIST] differential IBIS model generation -
» [SI-LIST] Career Advice for a junior EE -
» [SI-LIST] Re: creating differential IBIS files -
» [SI-LIST] Re: Question on 2D field solver -
» [SI-LIST] creating differential IBIS files -
» [SI-LIST] Question on 2D field solver -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: Differential volt meters -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Contract position for Sr SI Engr, in San Jose, CA -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] PCB simulation--PCB SI,Hspice,speedXP,HFSS,ADS... -
» [SI-LIST] Re: PCB simulation -
» [SI-LIST] Differential volt meters -
» [SI-LIST] PCB simulation -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Networking over Power-lines; Meeting, Santa Clara Valley EMC Society, IEEE -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] Re: DDR SDRAM signal routing -
» [SI-LIST] DDR SDRAM signal routing -
» [SI-LIST] RMCEMC October meeting slides available -
» [SI-LIST] Re: question about caculation the emitter follower output quiescent power -
» [SI-LIST] Looking for SI Job in India/US/Germany. -
» [SI-LIST] Re: self-destructive -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Frequency v/s Time Domain analysis -
» [SI-LIST] Frequency v/s Time Domain analysis -
» [SI-LIST] Re: Windows-based schematic editors -
» [SI-LIST] Re: Windows-based schematic editors -
» [SI-LIST] Windows-based schematic editors -
» [SI-LIST] Looking for Temporary/Permanant Opportunity in Bay Area -
» [SI-LIST] self-destructive -
» [SI-LIST] more soures of error in scope measurements -
» [SI-LIST] Re: looking for Bradley Henson and Michael Greim -
» [SI-LIST] Re: Delay line -
» [SI-LIST] Mentor Graphics Users -
» [SI-LIST] Sr. level Career Opportunity at Altera -