[SI-LIST] Re: DDR SDRAM signal routing
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: <leeritchey@xxxxxxxxxxxxx>, "Tom Biggs" <tbiggs@xxxxxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 8 Nov 2004 12:23:41 -0800
Hi Folks,
As frequency bins move upward you find new sources of SI issues even in
legacy DDR2/3 topologies. This along with subtle changes in buffer
designs and SDRAM module design require extensive frequency domain and
time domain simulations be done for every new DDR2/3 generation.
Fortunately, the mainstream memory controller vendors do all of this for
the end users and provide guidelines which if followed allow the
associated platform designs to be launched successfully without
simulation. A lot of analysis also goes into the JEDEC raw card
specifications to ensure the resident portion of the topologies are
optimized. So in most cases the end user does not need to simulate. Just
follow the guidelines.=20
Intel provides such guidelines and only recommends simulation when the
design deviates from our assumptions in terms of platform stackup, bus
lengths, and/or routing geometries. We try to provide a guaranteed
solution space which is adequate to allow our customers to build their
full line of boxes and get to market without extensive amounts of
simulation. Of course most big system houses have simulation resources
and expertise, but its not necessarily required unless the design is
unique in some way. Where simulation is needed is for people doing
non-standard applications using non-PC form factors and/or memory down
on the motherboard, etc... Another can of worms applies to folks using
dual stripline stackups where layer to layer coupling is not zero, or
where pure orthogonal routing rules can generate higher than expected
via counts. In these cases auxiliary simulation should be performed. =20
Brian P. Moran=20
Calistoga SIE Kit Leader=20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Monday, November 08, 2004 10:33 AM
To: Tom Biggs; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR SDRAM signal routing
All you have to do then, is trust those simulations. Based on the
accuracy of the average application note, is that a good thing to do?
Lee W. Ritchey
Speeding Edge
P. O. Box 2194
Glen Ellen, CA 95442
Phone- 707-568-3983
FAX- 707-568-3504
I just used the energy it took to be angry to write some blues.
Count Basie
> [Original Message]
> From: Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Date: 11/8/2004 10:14:43 AM
> Subject: [SI-LIST] Re: DDR SDRAM signal routing
>
> I'm going to play devil's advocate here just to get people thinking.
> (Note that I simulate the DDR designs I've done).
>
> Ed says "The driving force behind all this is time to market and=20
> system reliability."
>
> There is one other force: cost. These days we can be easily outsourced
> if we are too expensive to our bosses.=3D20
>
> How many IBM PowerPC 440GX (now AMCC's chip) designs have been done?=20
> How many times have people simulated them and come up with design=20
> guidelines that will work? Yes, many of these designs are different=20
> from each other, but I would bet that many of them are EXACTLY the=20
> same. Do we need 100 engineers to simulate the exact same thing 100=20
> times to come up with 100 identical sets of routing rules?=3D20
>
> If AMCC ran lots of simulations, then came out with a set of strict=20
> routing rules for some typical embedded 440GX applications, then=20
> someone should be able to design a board with these rules and not have
> to run simulations. Reliability should be fine if they do their job=20
> right, time to market will be short, and cost will be low.
>
> -tom
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx=20
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Ed Sayre III
> Sent: Monday, November 08, 2004 9:33 AM
> To: pm_norge@xxxxxxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DDR SDRAM signal routing
>
>
> Peter,
> You NEED to run simulations. I have worked on DDR SDRAMs=20
> architectures=3D20 for many years now and every one was slightly=20
> different. You can benefit=3D20 greatly from simulations since it=20
> generates your skew budget, component=3D20 placement and proper=20
> termination among other design points. If you=3D20 management tells =
you
> that they are willing to spend the money on repeated=3D20 turns, where =
> you may or may not find the right answer, then you are wasting=3D20 =
your
> money. Either hire a consultant with experience in the area of DDR
>
> memory or develop your own in house expertise. There are many people=20
> and=3D20
> products available right now. The driving force behind all this is
> time=3D20
> to market and system reliability.
>
> Good luck
> -Ed Sayre
>
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> NORTH EAST SYSTEMS ASSOCIATES, INC
> =
-------------------------------------=3D20
>
> "High Performance Engineering & Design"
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Dr. Edward Sayre 3rd e-mail: esayre3@xxxxxxxx
> NESA, Inc. http://www.nesa.com/
> 5 Lan Drive, Suite 200 Tel +1.978.392-8787 x 218
> Westford, MA 01886 USA Fax +1.978.392-8686
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
> At 09:32 AM 11/8/2004 +0000, you wrote:
> >I have been designing different kinds of electronic products, but=20
> >never
>
> >a DDR SDRAM interface with 16 memory chips (MT46V64M8, 512Mb =
chip,=3D20
> >8-bit @ 167MHz)and 2 ECC chips (same type).
> >
> >Between the processor (IBM PowerPC 440GX) and memory chips there=20
> >are=3D20 only the transmission lines and series termination resistors =
> >(25Ohm=3D20 close to the processor). I do not have the possibility to =
> >run=3D20 simulations, so it's learning by doing.
> >
> >The data lines are around 60-70mm and the address line around=20
> >250mm!!!=3D20 long. I'm afraid I will get serious SI problems with=20
> >this=3D20 configuration. I read some Appnotes but I could really use=20
> >some help=3D20 from experienced SI designers. What kind of =
termination=20
> >do I really=3D20 have to implement and what do I have to look out =
for?
> >
> >Thanks in advance
> >Peter
> >
> >_________________________________________________________________
> >Last ned MSN Messenger gratis http://www.msn.no/computing/messenger=20
> >-=3D20 Den korteste veien mellom deg og dine venner
> >
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