[SI-LIST] Re: DDR SDRAM signal routing
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: weirsp@xxxxxxxxxx
- Date: Tue, 09 Nov 2004 00:44:29 -0500
I'd second what Steve says. In my experience, just because an
application note says it's so, don't make it so. The problem with the
simulations (and app notes) of others are those pesky little unstated
assumptions. Sometimes they are unstated yet still considered in the
analysis. Sometimes they are unstated and were not considered. And
other times they are unstated and what was considered is just plain
wrong. Few if any application notes and design guides explicitly state
all the assumptions used. In fact, many of the assumptions are
considered proprietary by semiconductor companies. (When was the last
time you performed an analysis on a processor bus and included the
tester guard band for the processor and the controllerin your timing
analysis?)
The bottom line: If you want explicit control over all assumptions in
your system (and therefore want to take responsibility for engineering
of that system) then you will roll your own simulations and perform your
own analysis .... or suffer the consequence. Unless, of course, you can
get a semiconductor to certify that their application notes or design
guidelines are error free.
Y'all might want to take some time and read the legal disclaimers. They
are there for a reason.
regards and happy simulating,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
(503) 750-6481 Cellular
http://www.teraspeed.com
Teraspeed is the registered service mark of
Teraspeed Consulting Group LLC
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